Calibre xRC Parasitic Extraction

Duration:  1 day
Pricing:  $6000 NTD
Course Part Number: 217011

課程簡介

• 瞭解展平式與階層式Calibre xrc的設計流程
• 瞭解Calibre xrc的功能
• 瞭解如何執行最上層寄生參數摘取
• 瞭解如何執行第N層寄生參數摘取
• 瞭解如何對選擇的電路執行寄生參數摘取
• 瞭解如何執行Calibre xrc-PX（傳統展平模式）寄生參數摘取，無論是集總值
• 或分散值（lumped or distributed）
• 使用階層式資料庫查詢伺服器（Hierarchical Database Query Server）讀取階層
• 資料庫內容
• 瞭解和使用RC-Reduction，它是簡化寄生參數網路清單的工具  
• 瞭解SVRF寄生參數規則的組織、功能和特色，以及這些規則如何共同完成
• 實際的寄生參數摘取工作

適合對象

Calibre xrc工具使用者和程式設計人員 

預備知識

下列是必須擁有的預備知識：

• 已完成Calibre/ICverify Writing Training Workshop訓練課程，並擁有它所須的全部預備知識
• 已完成Using Calibre訓練課程

下列是建議擁有的預備知識/

• 瞭解積體電路的寄生參數摘取，特別是導線的部份
• 積體電路佈局技術和程序的知識
• 撰寫驗證規則的經驗

Course Overview

Post-layout simulation is both necessary and expensive. As process nodes shrink, the job of extracting the parasitics required for post-layout simulation is becoming both more critical and more difficult. In-house expertise and foundry-supplied PDKs are no longer the solution; they are the starting point. Performing extraction using Calibre xRC requires that you fully understand the many trade-offs you must make as well as the analysis needs presented by your designs. This course presents the most in-depth coverage of these topics available, extending your knowledge base far beyond existing documentation. Attendees should see immediate ROI in terms of both ramp-up time with the Calibre xRC tools and effectiveness.
 
Hands-on lab exercises will reinforce lecture topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. Upon completion of this course, students will understand the many trade-offs required to address the analysis needs presented by cutting edge designs and processes.

You will learn to

• Generate extracted netlists in six standard formats.
• Take advantage of the Calibre xRC 3-stage extraction process to generate multiple parasitic networks from a single extraction run.
• Leverage design hierarchy to obtain accurate results while keeping netlists manageable.
• Run Calibre xRC using the mode of your choice: GUI or batch.
• Review and interpret extraction results.
• Use advanced reduction techniques to minimize netlist size while maintaining a high level of accuracy.
• Customize foundry-supplied calibrated rules.
• Perform multi-corner extraction representing any or all of the process corners modeled by your foundry.
• Extract accurate parasitics in the presence of in-die variation or metal fill.
• Tailor your extraction runs to fit your design type (digital, memory, and analyog/RF and mixed signal) and process.

Hands-On Labs

Throughout this course, hands-on lab exercises provide you with practical experience using Calibre xRC under the guidance of our expert instructors. Topics include:

• Running Calibre xRC in either Batch or GUI mode.
• Interpreting transcripts and reports.
• Cross-probing parasitics in an open layout
• Exploring possible treatments for hierarchical designs, from flat to full hierarchical to hybrid.
• Generating extracted netlists in a variety of formats.
• Running simulations to compare pre-and post-layout netlists to reduced netlists.
• Working with a foundry-supplied PDK .
• Modifying PEX rules to avoid double counting of device parasitics.

Audience

This course is designed for:

• Layout Designers
• CAD Engineers
• Circuit Designers
• Silicon wafer fabrication teams needing to write, run circuit simulations, set-up or otherwise interpret Calibre xRC. This course should meet the needs of an audience of specialists who have knowledge of VLSI design. It is intended for users of xCalibre, Arcadia, StarRC, as well as, users who are new to parasitic extraction.

Prerequisites

• Calibre nmDRC/nmLVS training
• Basic knowledge of circuit simulation
• Ability to read circuit schematics
• Knowledge of layout verification concepts and tools

Key Topics

• Factors that Impact Extraction
• Types of Parasitic Networks
• Invoking Calibre xRC from the PEX GUI or Command Line
• Basic Extraction Work Flow Scenarios
• Factors that Impact Run Time
• Setting Up Calibre xRC for Best Performance
• Reading Reports and Transcripts
• Cross-Probing Hierarchical Parasitic Results
• Leveraging Hierarchy: Flat, Gate-Level, Full Hierarchical, and Hybrid Extractions
• Extracting Selected Nets
• Generating a Layout Based or Source Based Netlists
• Reduction Techniques
• Factory Recommended Reduction Strategies
• Reduction with Metal Fill
• Extraction Strategies for Memory Designs, Digital Designs, and Analog/RF Mixed-Signal Designs
• Working with Encrypted Rule Files
• Avoiding Double Counting of Capacitance
• Compensating for In-Die Variation
• Setting Up for Noise Analysis
• Setting Up for IR Drop Analysis