IC Design Flow With ICstudio

Duration:  4 days
Pricing:  $24000 NTD
Course Part Number: 225571

Description

This course will provide all the knowledge needed to apply the power of ICstudio, Mentor’s integrated IC design environment, to your most challenging VLSI designs.  As you progress through the course you will acquire the skills needed to manage your IC design project, capture and simulate your design, create the layout for your chip, use advanced interactive and automatic routing and floorplanning tools, perform DRC and LVS verification, and use extracted parasitic data in post-layout simulation.  The course addresses both analog and mixed-signal designs and provides everything you need to come up to speed quickly in this comprehensive IC design environment.

You will learn how to

• Create and modify ICstudio projects
• Create and edit hierarchical schematics
• Import HDL descriptions for design elements
• Set up and run analog simulations
• Create and simulate mixed-signal designs
• Create and edit hierarchical IC layouts
• Use Schematic-Driven Layout (SDL) tools to automatically construct layouts
• Add layout routing using interactive and automatic routing tools
• Plan top-level block size and placement using comprehensive floorplanning tools
• Verify layouts using Calibre DRC/LVS
• Extract parasitic data and use extracted parasitic data in simulations
  

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using ICstudio under the guidance of our expert instructors. Hands-on lab topics include:

• Setting ICstudio preferences
• Creating projects in ICstudio
• Project maintenance in ICstudio
• Schematic capture
• Setting up and running analog simulation
• Working with mixed-signal designs
• Simulating a mixed-signal design with ADMS
• Basic polygon editing skills
• Working with hierarchical layouts
• Automatically generating device layout and interconnection (SDL)
• Creating, sizing, and placing hierarchical blocks
• Finding layout design rule errors with Calibre DRC
• Verifying layout connectivity with Calibre LVS
• Extracting and simulating with parasitic data
  

Audience

• Front-end design engineers
• IC layout engineers and designers
• CAD engineers and managers who will be responsible for integrating ICstudio into their design flow
• Members of CAD support groups who are responsible for increased productivity of VLSI design teams

Prerequisites

• Basic knowledge of IC design and layout techniques and procedures (helpful but not required)
• Familiarity with UNIX

Key Topics

• ICstudio core concepts
• Project management with ICstudio
• Design Arcgitect-IC schematic capture environment
• Creating and editing schematics
• Setting up and running analog simulation
• Schematic capture - advanced topics
• Mixed-signal simulation
• IC Station overview
• IC Station polygon editing
• IC Station hierarchical editing
• Schematic-Driven Layout (SDL) in IC Station
• Interactive layout routing with IRoute
• Automatic routing with ARoute
• Floorplanning with ICassemble
• Layout verification with Calibre DRC/LVS
• Parasitic extraction with Calibre xRC