TAU - Timing Analysis

Timing driven design begins with a comprehensive timing analysis of the design to determine how much margin is available while meeting setup and hold constraints. This available margin is the "slack" that can be used by the PCB interconnect. These slack times are then forward annotated to ICX and are loaded into the constraint engine as the PCB timing rules which guide floorplanning and routing.

After the board is routed, the actual interconnect delays are back annotated to Tau and a complete timing analysis of the design is performed to ensure that all timing constraints are met. This complete design flow ensures that your design will operate at speed with the right amount of margin over all process variations.

Designed from the ground up for PCB and system level timing analysis, Tau is the market leader in timing analysis. Powerful capabilities within Tau give the designer the capability to analyze timing issues in designs ranging from the simplest to the most complex timing paths.

See how using Tau can improve your high-speed design process:

• Powerful and easy to use
  • Easy to use spreadsheet based interface allows quick access to powerful analysis capabilities
• Min/max timing verification
  • Ensures the design will operate over all possible process spreads
• Advanced symbolic timing methodology
  • Restricts analysis to relevant paths, while eliminating the false paths often reported by standard static timing tools
• Generation of routing constraints
  • When used with ICX, it facilitates a timing driven design process
• Easy model generation
  • Spreadsheet based modeling tool
  • Direct import of Timing Designer and TDML files

Intuitive graphical interface presents timing violations in easy-to-read spreadsheets, integrated with waveform views of the data.