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ReqTracer for FPGA/ASIC Design Assurance
This course will help students learn how to automate the tracing of design requirements to design and test data associated with an FPGA or ASIC design. This class is targeted at engineers and technical managers tasked with carrying out design assurance activities needed to certify for customers or regulatory agencies that the device performs its intended function.
More upcoming dates (1 total)
HDL Designer Series
This class teaches you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lecture takes you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior.
More upcoming dates (2 total)
ModelSim / Questa Core: HDL Simulation
ModelSim / Questa Core: HDL Simulation teaches you to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.
More upcoming dates (5 total)