Questa & ModelSim
Available Courses: Register today!
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ModelSim / Questa Core: HDL Simulation
ModelSim / Questa Core: HDL Simulation teaches you to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. More upcoming dates (5 total)
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6/20/13 | Meudon, FR | ||||||||||
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ModelSim / Questa Core: Advanced Topics
ModelSim® / Questa® Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim / Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence of simulation thoroughness and completeness. More upcoming dates (5 total)
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7/10/13 | Online | ||||||||||
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PSL: Assertion Based Verification with Questa
This class introduces you to the concept of Assertion Based Verification (ABV), and gives you the tools to start using the techniques in your design and verification tasks. The class introduces the PSL language, Accellera Version 1.1, so that you can write the properties and assertions for your code, and also considers simulating with the assertions using Questa and its assertion capabilities. It shows how Questa's assertion capabilities combine with its other aspects to help you debug your design efficiently. You will also be introduced to the Assertion Thread Viewer, and its use in debugging assertion issues. More upcoming dates (2 total)
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7/15/13 | Online | ||||||||||
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Questa Essentials
This course will teach you the benefits of Questa’s advanced verification environment. Lectures include advanced functional verification topics such as constrained-random stimulus generation, functional coverage, code coverage, and SystemVerilog assertions. More upcoming dates (1 total)
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11/18/13 | Herzliya, IL |
Available by request
These classes can be scheduled at your convenience, upon request, at a Mentor training center or your company site. We can also customize a course to fit your needs.
Contact us
Mentor Graphics Education Services
1-800-345-2308
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