Instructor-led Training (Classroom and Live Online)
Mentor's instructor-led training is available in our training centers or through our Live Online remote program. Private training, at your site or ours, is available by request. Request private training
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Tessent Diagnosis will teach you to capitalize on the methods of defect discovery on failing devices in a production environment. Using the defect reports from YieldAssist you will be able to plan the analysis process in determining the root cause of failure, reducing time and improving your hit rate. With the correlation between the 'Logical netlist' and the Physical layout you will have a indication of the most likely area where to begin the failure analysis.
More upcoming dates (5 total)
The Tessent IJTAG course drives the development of your skills and knowledge using Instrument Connectivity Language (ICL) in order to describe the interfaces and connectivity in your design
More upcoming dates (2 total)
The Tessent® MemoryBIST course will help you understand how to implement DFT for memory test. You will be introduced to Tessent™ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow.
More upcoming dates (6 total)
Tessent MemoryBIST and LogicBIST
The Tessent® Memory BIST and Logic BIST course will help you understand how to implement DFT for memory and logic test. You will be introduced to Tessent technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow.
More upcoming dates (3 total)
Tessent Scan and ATPG
The Tessent®: Scan and ATPG course will drive the development of your skills and knowledge in scan and ATPG design processes utilizing the Tessent Scan point tool, Tessent FastScan™, Tessent TestKompress®, and the Tessent point tool DFTVisualizer.
More upcoming dates (10 total)
Tessent TestKompress and Advanced Topics
This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues.
More upcoming dates (9 total)