Available Courses: Register today!
|Course Title||Next Date||Location|
This course will help you understand how to implement DFT for memory test. You will be introduced to Tessent™ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit.
More upcoming dates (8 total)
|3/19/14||Hsinchu City, TW|
Tessent Scan and ATPG
The Tessent®: Scan and ATPG course will drive the development of your skills and knowledge in scan and ATPG design processes utilizing the Tessent Scan point tool, Tessent FastScan™, Tessent TestKompress®, and the Tessent point tool DFTVisualizer.
More upcoming dates (10 total)
|3/25/14||Hsinchu City, TW|
Tessent TestKompress and Advanced Topics
This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues.
More upcoming dates (6 total)
|3/27/14||Hsinchu City, TW|
Tessent Diagnosis will teach you to capitalize on the methods of defect discovery on failing devices in a production environment. Using the defect reports from YieldAssist you will be able to plan the analysis process in determining the root cause of failure, reducing time and improving your hit rate. With the correlation between the 'Logical netlist' and the Physical layout you will have a indication of the most likely area where to begin the failure analysis.
More upcoming dates (1 total)
Available by request
This class can be scheduled at your convenience, upon request, at a Mentor training center or your company site. We can also customize a course to fit your needs.