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Calibre Advanced Topics: Double Patterning

Categories: Calibre

Starting with the 20nm processing node, the use of two masks to print a single layer becomes a requirement because of lithography issues. This course will help you understand the impact of double patterning on your designs and how to use Calibre to find and fix layout problems associated with this approach. View course details ↓


Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Apr 16–172015 Fremont California 9–5 PM
English 1,600 USD Register
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Course Highlights

Foundries have already modified their rule decks to support the use of double patterning and will require all 20nm (and smaller) customers to use this technique. There are many implications for chip designers and CAD support teams when double patterning is employed. This course will help users understand those implications and show them how to create designs that are compatible with double patterning using foundry-provided rule decks and Calibre.

You will learn how to:

  • Explain the need for double patterning
  • Describe the various techniques employed to compensate for double patterning implications
  • Invoke Calibre to identify and potentially repair double patterning layout problems
  • Interpret Calibre output to locate and understand problematic layout geometries
  • Modify layouts to reduce or eliminate double patterning problems
  • Understand basic Calibre SVRF code used to find and fix double patterning layout issues

Hands-on labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Calibre software. Hands-on lab topics include:

  • Viewing “bad” mask contours
  • Running a Calibre double patterning example
  • DRC spacing rule implications
  • Running the new Calibre DP flow
  • Exercising different decomposition flows
  • User-defined color choices
  • Dealing with hierarchy
  • Recommended flows
  • Interpreting DP results in RVE
  • Using DP with place and route
  • Using DP with parasitic extraction

Course Information


Completion of the Calibre nmDRC/nmLVS class is very highly recommended

Completion of the Calibre DRC/LVS rule-writing course is also highly recommended

Thorough knowledge of IC layout techniques and procedures

Experience with an IC layout editing tool

Familiarity with UNIX

Good understanding of layout verification concepts and experience with layout verification tools

Course Part Number
  • Classroom: 254831
  • Live online: 254832
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