Calibre Advanced Topics: nmLVS Debug Case Studies
Layout Versus Schematic (LVS) verification has always played a critical role in the IC design process. Calibre nmLVS continues to be the pre-eminent tool for this task. Recent Calibre enhancements have significantly extended the tool’s capabilities and have helped to streamline the LVS debugging task. This course will introduce you to all of these new features through a series of LVS case studies. View course details ↓
Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.
|Sep 22–23||Bangalore||9:30–5:30 PM
|Oct 3||Hsinchu City||9–5 PM
|Chinese (Mandarin)||300 USD||Register|
|Nov 6–7||Singapore||9–5 PM
|Don't see the class you need? Request a class|
Each case represents a unique LVS problem and includes a step-by-step solution. Solutions will be demonstrated in real time through actual tool execution, allowing students to experience each step and to interact with the instructor to explore alternatives.
Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors. Each exercise will provide the opportunity to apply problem-solving skills and utilize tool features presented in the case studies.
You will learn how to
- Invoke the new LVS Debug environment
- Configure the LVS Debug environment
- Display LVS results
- Employ the new built-in schematic viewer
- Use the new error analysis feature to generate fix suggestions
- Specify new error highlight options
- Apply new short isolation techniques
- How to use the new LVS Debug GUI features
- Debugging netlist problems
- Debugging connectivity problems
- Debugging problems related to shorted nets
- Debugging device-related problems
- And more …