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Calibre Fundamentals: Writing DRC/LVS Rules

Categories: Calibre

This course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors. View course details ↓


Live Online classes deliver all the interactivity and depth of the traditional classroom, from the convenience of your own computer, with hands-on exercises and course materials. Learn more about Live Online training

Date Time Language Price
Mar 30–Apr 82015 8–2 PM
English 3,200 USD Register


Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Apr 20–232015 Bangalore India 9:30–5:30 PM
English 78,840 INR Register
Apr 21–242015 El Segundo California 9–5 PM
English 3,200 USD Register
Apr 28–302015 Hsinchu City Taiwan 9–5 PM
Mandarin 34,650 TWD Register
Jun 15–182015 Meudon France 9–5 PM
French 2,960 EUR Register
Jun 23–262015 Fremont California 9–5 PM
English 3,200 USD Register
Jul 20–232015 Bangalore India 9:30–5:30 PM
English 78,840 INR Register
Aug 11–142015 Fremont California 9–5 PM
English 3,200 USD Register
Nov 16–192015 Bangalore India 9:30–5:30 PM
English 78,840 INR Register
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Course Highlights

You will learn how to

  • Write DRC rules that perform a full complement of layout dimensional checks
  • Write specification statements to control DRC output
  • Use Boolean and topological operators to derive new layer data
  • Debug rule files
  • Write polygon-directed and edge-directed checks
  • Write basic and enhanced antenna rule checks
  • Improve DRC run-time efficiency
  • Write equation-based DRC rule checks
  • Create and use layer properties
  • Write rules to establish layout connectivity
  • Write rules to recognize different devices such as MOS transistors, resistors and capacitors of different types, bipolar transistors etc. in the layout
  • Extend the set of built-in device templates to include your own custom devices
  • Extract various properties such as width, length, resistance and capacitance of recognized devices, using the Built-in property language within Calibre nmLVS TM and compare these values with those specified in the source netlist
  • Effectively utilize the text present in the GDSII layout database, and supplement it with text supplied through the rule file to annotate nets and ports • Optimally use the various Calibre statements that deal with net and port names in the layout
  • Write various LVS specification statements that control how the layout netlist extracted from the layout database is compared to the source netlist
  • Effectively block out selected cells during the LVS netlist comparison process
  • Call Calibre TVF routines from within device property computation functions
  • Access layout property data from within device property computation functions

Hands-on labs

  • Preparing the Rule File and Running Calibre
  • Viewing DRC and LVS Results
  • Using the Online Documentation
  • Writing Layer Definitions
  • Writing DRC and LVS Specification Statements
  • Writing and Testing Dimensional Rule Checks
  • Designing and Testing Derived Layer Statements
  • Writing Polygon-directed Rule Checks
  • Designing and Testing Edge and Error-directed Rule Checks
  • Creating and Using Layer Properties
  • Writing and Testing Connectivity Statements
  • Designing and Testing Antenna Rule Checks
  • Taking Advantage of Hierarchy
  • Setting LVS Report Options
  • Finding Soft Connections
  • Creating and Naming Ports
  • Inserting Text Objects Into a Layout Using the Rule File
  • Writing Device Recognition Statements
  • Specifying Custom User-Defined Devices
  • Using the Built-In Language to Define Device Properties
  • Writing TVF code to generate a DRC rule file

Course Information


Completion of the Calibre nmDRC/nmLVS class is very highly recommended

Thorough knowledge of IC layout techniques and procedures

Experience with an IC layout editing tool Good understanding of SPICE netlists

Familiarity with UNIX

Good understanding of layout verification concepts and experience with layout verification tools

Course Part Number
  • Classroom: 058450
  • Live online: 239707
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