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Calibre TVF

Categories: Calibre

This course will help you unleash the powers of TVF to make your SVRF files more compact, easier to maintain, and more powerful. Using several examples, you will learn how to incorporate TVF functionality into your rule files to make writing SVRF rules easier. View course details ↓

Classroom

Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Jan 72015 Hsinchu City Taiwan 9–5 PM
CST
Mandarin 300 USD Register
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Course Highlights

 

You will learn how to

  • Use Calibre TVF to simplify rule writing.
  • Create rule files that are smaller, more flexible, and easier to maintain.
  • Write Compile-Time TVF to generate SVRF rule files.
  • Add Runtime TVF to SVRF rule files for increased functionality

Hands-on labs

  • Review of Tcl concepts
  • Performing verification using Runtime and Compile-Time TVF
  • Using Compile-Time TVF to create DRC rulechecks
  • Debugging Compile-Time and Runtime TVF
  • Writing TVF Functions using Runtime TVF

Key topics

  • Review of Tcl syntax and concepts
  • Using Compile-Time Calibre TVF
  • Enhancing existing SVRF rule files with TVF
  • Writing and debugging Compile-Time TVF code
  • Using looping structures to automate generation of large amounts of SVRF code
  • Writing and calling procedures to produce derived layers or rule checks
  • Controlling rule file contents from an external file
  • Writing Runtime TVF functions
  • Adding TVF comments for readability and ease of maintenance
  • Using Runtime Calibre TVF

Course Information

Intended for

Experienced IC Layout Engineers and Layout Verification specialists who will write, maintain, support, and optimize various DRC and LVS rule decks in their organization

Experienced CAD Engineers and Managers who will be responsible for integration of the Calibre toolset in their design flow

Experienced CAD specialists who interface with various foundries such as TSMC, UMC, Chartered, and integrate the rule decks supplied by these foundries into the verification flow

Layout Verification specialists in foundries who are responsible for generating qualified rule decks in their various process offerings

Prerequisites

Completion of the Calibre Rule Writing class very highly recommended

Thorough knowledge of IC Layout techniques and procedures

Experience with an IC layout editing tool

Familiarity with UNIX

Good understanding of layout verification concepts and experience with layout verification tools

Experience programming in any language. (Familiarity with Tcl is very helpful, but not absolutely required.)

Course Part Number
  • Classroom: 234638
  • Live online: 241764
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