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Calibre xRC Parasitic Extraction

Categories: Calibre

This course presents the most in-depth coverage of these topics available, extending your knowledge base far beyond existing documentation. Attendees should see immediate ROI in terms of both ramp-up time with the Calibre xRC tools and effectiveness. View course details ↓

Classroom

Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Jan 62015 Hsinchu City Taiwan 9–5 PM
CST
Mandarin 300 USD Register
Jan 13–142015 Fremont California 9–5 PM
PST
English 1,600 USD Register
Jan 15–162015 Beijing China 9–5 PM
CST
Malayalam 5,600 CNY Register
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Course Highlights

Post-layout simulation is both necessary and expensive. As process nodes shrink, the job of extracting the parasitics required for post-layout simulation is becoming both more critical and more difficult. In-house expertise and foundry-supplied PDKs are no longer the solution; they are the starting point. Performing extraction using Calibre® xRC™ requires that you fully understand the many trade-offs you must make as well as the analysis needs presented by your designs.

Upon completion of this course, students will understand the many trade-offs required to address the analysis needs presented by cutting edge designs and processes.

You will learn to

  • Generate extracted netlists in six standard formats.
  • Take advantage of the Calibre xRC 3-stage extraction process to generate multiple parasitic networks from a single extraction run.
  • Leverage design hierarchy to obtain accurate results while keeping netlists manageable.
  • Run Calibre xRC using the mode of your choice: GUI or batch.
  • Review and interpret extraction results.
  • Use advanced reduction techniques to minimize netlist size while maintaining a high level of accuracy
  • Customize foundry-supplied calibrated rules.
  • Perform multi-corner extraction representing any or all of the process corners modeled by your foundry.
  • Extract accurate parasitics in the presence of in-die variation or metal fill.
  • Tailor your extraction runs to fit your design type (digital, memory, and analyog/RF and mixed signal) and process.

Hands-on labs

  • Running Calibre xRC in either Batch or GUI mode.
  • Interpreting transcripts and reports.
  • Cross-probing parasitics in an open layout.
  • Exploring possible treatments for hierarchical designs, from flat to full hierarchical to hybrid.
  • Generating extracted netlists in a variety of formats.
  • Running simulations to compare pre-and post-layout netlists to reduced netlists.
  • Working with a foundry-supplied PDK .
  • Modifying PEX rules to avoid double counting of device parasitics.

Course Information

Prerequisites

Calibre nmDRC/nmLVS training

Basic knowledge of circuit simulation

Ability to read circuit schematics

Knowledge of layout verification concepts and tools

Course Part Number
  • Classroom: 217011
  • Live online: 241763
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