CES for Board Station XE Flow
Categories: Board Station
This course is designed to cover all the necessary skills required to use CES efficiently and effectively in Board Station XE design flow. View course highlights ↓
|Jun 27–28||Meudon||9–5 PM
|Don't see the class you need? Request a class|
CES is a Constraint Editor System, which gives you the ability to define and refine design constraints in a common environment that is accessible from many Mentor Graphics Corporation front-end and back-end design systems.
The labs in the course allow you to gain hands-on experience with the tool, defining both mechanical and high-speed constraints to meet today’s challenging PCB designs.
You will learn how to
- Define the main concepts and constraints hierarchy of CES.
- Enable CES as a constraint system in Board Station flow.
- Find and filter data in the design database.
- Navigate and manipulate the constraints hierarchy.
- Use the spreadsheets, toolbars, preferences, and options efficiently.
- Partition the design data using Net Classes, Constraint Classes and Schemes.
- Set up mechanical constraints such as trace widths, via assignments and clearances.
- Assign physical high-speed constraints including minimum and maximum delays, matched delays, delay formulas, custom and complex topologies, differential pairs, and parallelism rules to nets or group of nets.
- Auto-route the constrained nets and evaluate the routing results.
- Reuse already defined constraints in the same design or other designs using Constraint Templates.
- Adopting CES and synchronizing databases in Design Architect/Board Architect to Board Station XE Flow
- User Interface
- Customizing the Windows Display
- Use the CES Browser and the Spreadsheets
- Edit Data in Spreadsheets
- Interface with the PCB Data
- Creating Net Class and Schemes
- Create Schemes
- Create and populate Net Classes
- Setting Up Mechanical Constraints
- Set up Trace and Via Properties
- Set up Clearance Rules
- Creating Constraint Classes
- Setting up Differential Pairs and Net Properties
- Create differential pairs
- Set differential pair constraints
- Assign custom topologies
- Assign complex topologies
- Setting up delays and parallelism
- Assign length and match group constraints
- Set up delays formulas
- Set up parallelism rules
- Route delay and length constrained nets
- Using Constraint Templates
- Import and export Constraint Templates
- Test Constraint Templates
- Assign Constraint Templates to nets
- CES Overview
- CES in the flow
- CES User Interface
- Net Classes and Schemes
- Setting up Mechanical Constraints
- Creating Constraint Classes
- Net Properties and Differential Pairs
- Delays and Parallelism
- Using constraint templates
PCB Design Engineers
PCB layout personnel
Signal Integrity Engineers
This course is for anyone who works with constraint-driven high-speed PCB designs.
Students should be familiar with at least one of the Mentor Graphics system design flows.
|Course Part Number||