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CES for Expedition PCB

Categories: Expedition/Xpedition

Using CES for Expedition┬«, learn to quickly define and refine design constraints accessible from many Mentor Graphics PCB design systems, to improve design accuracy. View course details ↓


Self-paced online training lets you acquire course skills any time, from any computer, complete with software access and hands-on lab exercises. Start your training within minutes of registration! Learn more about on-demand training

Date Language Price
Anytime! English 800 USD Register

Live Online classes deliver all the interactivity and depth of the traditional classroom, from the convenience of your own computer, with hands-on exercises and course materials. Learn more about Live Online training

Date Time Language Price
Feb 2–52015 8–2 PM
English 1,400 USD Register

Course Details

In this course, Mentor PCB design experts will teach you to use CES as a constraint system in the DxDesigner-to-Expedition PCB flow, giving you the detailed knowledge you need to define design constraints.

You will learn to quickly document your design constraints in a spreadsheet paradigm with formulas, references, hierarchy and reuse. Hands-on lab exercises will reinforce lecture topics and facilitate efficient constraint definition for complete design, e.g., complex buses, Gigabit channels, DDR, etc.

What you'll learn

Lecture/demonstration discussions will be followed by hands-on lab experiences to reinforce knowledge gained from the lecture material. This course steps you through the following lectures and exercises:

CES overview

  • Using the CES graphical user interface and customizing it
  • Define, navigate and manipulate constraints hierarchies in CES

Mechanical constraints

  • Partition design data using net classes, constraint classes and schemes
  • Set up mechanical constraints such as trace widths, via assignments, and clearances

High-speed constraints

  • Assign physical high-speed constraints such as minimum/maximum/matched delays, delay formulas, custom or complex topologies, differential pairs and parallelism rules to nets/net groups
  • Autoroute constrained nets and evaluate routing results

Design validation and constraint reuse

  • Validate the layout against constraints directly within the editor
  • Employ constraint templates to reuse already-defined constraints in other designs

Course Information

Intended for

PCB engineers and layout designers who want to increase productivity by adopting efficient, flow-wide constraint methodology


Familiarity with concepts of PCB design and technology

Course Part Number
  • Classroom: 236552
  • Live online: 239700
  • On-demand: 259649

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