FloTHERM PACK

Course Highlights

The main goals of the course are to make the student familiar with the operation and functionality of FloTHERM PACK, to provide a good understanding of different IC packaging families, characterization techniques, and the use of these representations in their FloTHERM thermal analysis models.

The course is arranged as follows:

• The course covers the documented lectures and hands-on tutorials, with demonstrations used to illustrate important points. The combination of these different formats is designed to show the student the range of functionality available in FloTHERM PACK, and how they can utilize the component models in the thermal analysis of IC packages used in the industry
• You will learn about the building blocks of typical IC packages, basic definitions such as case and junction temperature, JEDEC test environments and so on. Some traditional and advanced package families will be discussed in detail and the approach to their thermal characterization will be discussed. JEDEC standard test environments will be discussed in detail and you will be shown how FloTHERM PACK can be used to include standard packages in desired test environments
• The last section of the course will cover compact modeling of IC packages. The need and advantages of such compact models including two-resistor, multi-resistor and DELPHI style compact models will be covered, followed by a brief introduction to thermal characterization of IC packages.

What you will learn

In attending the training, you will learn the fundamental operation and functionality of the FloTHERM PACK software, including: IC package model creation methodology; creation of compact models; and their use in FloTHERM

Agenda

Lecture 1: Introduction to FloTHERM PACK

• History and background of IC packages
• Definition and importance of Case and Junction Temperatures
• Internal world of a typical package
• Industry standards (package outlines or styles, JEDEC)
• Packaging concepts

Lecture 2: Modeling Traditional Package Families

• Fine Pitch BGA
• Flip-Chip BGA
• QFN
• TSOP

Lecture 3: Modeling Advanced Package Families

• Chip-Scale Packages
• Micro-BGA
• Wafer-Scale BGA
• Stacked-Die Packages
• SIP’s
• Non-Uniform Dies

Lecture 4: JEDEC Test Environments and Modeling Package Environment

• JEDEC environments
• Obtaining 2-R values from JEDEC environments
• PCBs and heat sinks

Lecture 5: Compact Modeling of IC packages and Introduction to T3ster

• Two Resistor models, background and history
• Multi-Resistor models
• DELPHI Compact models. Methodology and benefits
• Introduction to T3Ster
• Characterization of IC packages using T3Ster