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Categories: FormalPro

FormalPro is the Mentor Graphics equivalence checking product for dramatically reducing the time required to verify ASICs and ICs. This class describes background and benefits of formal verification technology and how it applies to current ASIC design methodologies. It will teach you how to setup, compile and verify designs, and then debug and successfully correct design errors. View course details ↓

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Course Highlights

You will learn how to

  • Use FormalPro in graphical, command line and batch modes
  • Compile designs, specify black-box elements and set constraints
  • Match two designs and set compare points
  • Verify designs using FormalPro's multiple solve engines
  • Debug differences in your design using FormalPro's debug tool
  • Test design corrections using FormalPro's What-If Analysis tool
  • Compile and verify libraries

Hands-on labs

  • Formal verification introduction
  • Matching with FormalPro
  • Complex matching
  • Introduction to debug
  • Advanced debugging
  • Combining Libraries
  • Verify a Xilinx FPGA design

Key topics

  • Problems in verification today
  • Solutions offered by formal verification
  • Equivalence checking
  • Mixed language and mixed level capability
  • Tool stages
  • Comparison points
  • Matching (rule based, graph isomorphism, explicit)
  • Powerful solvers
  • GUI and batch mode
  • Reports
  • Syntax
  • Matching
  • Advanced User Rule Matching Controls
  • Heirarchical verification
  • Conditional equivalence
  • Advanced constraints
  • Black boxing
  • Solving
  • Debugging functional differences
  • Report generation
  • FormalPro's debug tool
  • "What if" analysis
  • Library formats supported
  • Built-in primitives
  • Modifying library cells
  • Combining libraries
  • Pre-compiling libraries

Course Information

Intended for

ASIC Design Engineers

Verification Engineers


Familiarity with ASIC design methodology

Familiarity with VHDL and/or Verilog hardware description languages

Course Part Number
  • Classroom: 210869

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