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HDL Designer Series

Categories: FPGA, HDL & Other Languages

This class teaches you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lecture takes you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior. View course details ↓

Online

Live Online classes deliver all the interactivity and depth of the traditional classroom, from the convenience of your own computer, with hands-on exercises and course materials. Learn more about Live Online training

Date Time Language Price
Mar 9–132015 9–3 PM
PDT
English 1,400 USD Register

Course Highlights

You will learn how to

  • Set up libraries to hold your designs
  • Model hierarchy and connectivity using block diagrams and IBD
  • Model finite state machines with state diagrams
  • Model sequential processes with flow charts
  • Model combinatorial circuits with truth tables
  • Create and edit component symbols
  • Generate HDL for your graphical/textual design
  • Compile your design for simulation
  • Simulate your design using ModelSim®
  • Animate and debug your design
  • Reuse components
  • Convert existing HDL designs into graphical/textual HDL Designer Series designs
  • Create test benches
  • Manage your design using version management
  • Ensure your design meets required design rules using DesignChecker
  • Interface with a wide range of downstream tools (compilers, simulators, and synthesis tools)
  • Trace requirement references between ReqTracerTM and HDL Designer

Hands-on labs

 

  • Import existing HDL code into HDL Designer
  • Create block diagrams, state machines, truth tables, and flow charts
  • Create control logic using state machines
  • Generate HDL for your design
  • Create a test bench using a flow chart to provide stimulus
  • Compile and simulate your design
  • Troubleshoot your design using animation
  • Place existing design elements into new designs
  • Implement Altera MegaWizard and Xilinx CoreGen components in your design
  • Import existing HDL design hierarchy into HDL Designer for visualization
  • Run DesginChecker and analyze results
  • Generate HTML documentation

Course Information

Prerequisites

Basic knowledge of FPGA and ASIC and design techniques and procedures

Reading knowledge of HDL languages (VHDL or Verilog)

Course Part Number
  • Classroom: 209128
  • Live online: 241391
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