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HyperLynx Advanced High-Speed PCB Analysis

Categories: Expedition, HyperLynx

This course will help you understand the application of HyperLynx SI to solve real world signal integrity problems. It covers two design areas in both pre- and post-layout: source-synchronous design analysis and SERDES design analysis View course highlights ↓

Online

Our instructor-led online classes offer all the benefits of classroom training without the travel. Participate in a live classroom experience, complete with hands-on exercises and course materials, directly from your office.

Date Time Language Price
May 5–92014 8–2 PM
PDT
English 2,100 USD Register

Classroom

Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Apr 23–252014 Longmont Colorado 9–5 PM
MDT
English 2,100 USD Register
Apr 28–302014 Bangalore India 9:30–5:30 PM
SGT
English 59,130 INR Register
Jun 23–252014 Singapore Singapore 9–5 PM
SGT
English 1,500 USD Register
Jul 22–242014 Munich Germany 9–5 PM
CEST
German 1,950 EUR Register
Aug 13–152014 Singapore Singapore 9–5 PM
SGT
English 1,500 USD Register
Oct 21–232014 Munich Germany 9–5 PM
CEST
German 1,950 EUR Register
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Course Highlights

You will learn how to

  • Explore and differentiate DDRx and SERDES designs
  • Apply signal integrity concepts to DDRx and SERDES designs
  • Analyze DDRx memory interface for signal integrity in pre-layout phase
  • Analyze crosstalk for single-ended and differential nets in DDRx designs
  • Perform timing analysis for DDRx memory interface
  • Set up and use DDRx wizard for post-layout analysis of DDRx memory interface
  • Generate Eye Diagrams in HyperLynx
  • Analyze loss for various configurations of SERDES channels in pre-layout phase
  • Perform post-layout analysis of SERDES channels
  • Use Fast Eye Diagram wizard for SERDES channels

Hands-on labs

  • Getting familiar with DDR2 and PCI Express designs
  • Pre-layout SI analysis of DDR2 memory interface
  • Pre-layout crosstalk analysis of DDR2 memory interface
  • Pre-layout timing analysis of DDR2 memory interface
  • Post-layout verification of DDR2 memory interface
  • Pre-layout analysis of SERDES channel
  • Post-layout verification of SERDES channel

Course Details

Prerequisites

Familiarity with High-Speed PCB concepts

Familiarity with the use of HyperLynx software. (Taking basic HyperLynx Signal Integrity class is preferred)

Familiarity with Windows operating systems

Course Part Number
  • Instructor-led: 234951
  • Live online: 241799
Products Covered
Guides
 
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