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IC Design Flow With Pyxis

Categories: Pyxis

IC Design Flow With Pyxis™ will provide all the knowledge needed to apply the power of Pyxis, Mentor’s integrated IC design environment, to your most challenging VLSI designs. The course covers the full IC design flow, from capture through final layout verification and analysis. View course details ↓

Classroom

Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Oct 7–102014 Tempe Arizona 9–5 PM
MST
English 3,200 USD Register
Dec 16–192014 Fremont California 9–5 PM
PST
English 3,200 USD Register
Feb 10–132015 Tempe Arizona 9–5 PM
MST
English 3,200 USD Register
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Course Highlights

As you progress through the course you will acquire the skills needed to manage your IC design project, capture and simulate your design, create the layout for your chip, use advanced interactive and automatic routing and floorplanning tools, perform DRC and LVS verification, and use extracted parasitic data in post-layout simulation. The course addresses both analog and mixed-signal designs and provides everything you need to come up to speed quickly in this comprehensive IC design environment.

You will learn how to

  • Create and modify Pyxis projects
  • Create and edit hierarchical schematics
  • Import HDL descriptions for design elements
  • Set up and run analog simulations
  • Create and simulate mixed-signal designs
  • Create and edit hierarchical IC layouts
  • Use Schematic-Driven Layout (SDL) tools to automatically construct layouts
  • Add layout routing using interactive and automatic routing tools
  • Plan top-level block size and placement using comprehensive floorplanning tools
  • Verify layouts using Calibre DRC/LVS
  • Extract parasitic data and use extracted parasitic data in simulations

Hands-on labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Pyxis software. Hands-on lab topics include:

  • Creating projects in Pyxis
  • Project maintenance in Pyxis
  • Schematic capture
  • Setting up and running analog simulation
  • Working with mixed-signal designs
  • Simulating a mixed-signal design with ADMS
  • Basic polygon editing skills
  • Working with hierarchical layouts
  • Automatically generating device layout and interconnection (SDL)
  • Creating, sizing, and placing hierarchical blocks
  • Finding layout design rule errors with Calibre DRC
  • Verifying layout connectivity with Calibre LVS
  • Extracting and simulating with parasitic data

Course Information

Intended for

Front-end design engineers

IC layout engineers and designers

CAD engineers and managers who will be responsible for integrating Pyxis into their design flow

Members of CAD support groups who are responsible for increased productivity of VLSI design teams

Prerequisites

Basic knowledge of IC design and layout techniques and procedures (helpful but not required)

Familiarity with UNIX
 

Course Part Number
  • Classroom: 254192
  • Live online: 254191
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