IC Design Flow With Pyxis

Course Highlights

As you progress through the course you will acquire the skills needed to manage your IC design project, capture and simulate your design, create the layout for your chip, use advanced interactive and automatic routing and floorplanning tools, perform DRC and LVS verification, and use extracted parasitic data in post-layout simulation. The course addresses both analog and mixed-signal designs and provides everything you need to come up to speed quickly in this comprehensive IC design environment.

You will learn how to

• Create and modify Pyxis projects
• Create and edit hierarchical schematics
• Import HDL descriptions for design elements
• Set up and run analog simulations
• Create and simulate mixed-signal designs
• Create and edit hierarchical IC layouts
• Use Schematic-Driven Layout (SDL) tools to automatically construct layouts
• Add layout routing using interactive and automatic routing tools
• Plan top-level block size and placement using comprehensive floorplanning tools
• Verify layouts using Calibre DRC/LVS
• Extract parasitic data and use extracted parasitic data in simulations

Hands-on labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Pyxis software. Hands-on lab topics include:

• Creating projects in Pyxis
• Project maintenance in Pyxis
• Schematic capture
• Setting up and running analog simulation
• Working with mixed-signal designs
• Simulating a mixed-signal design with ADMS
• Basic polygon editing skills
• Working with hierarchical layouts
• Automatically generating device layout and interconnection (SDL)
• Creating, sizing, and placing hierarchical blocks
• Finding layout design rule errors with Calibre DRC
• Verifying layout connectivity with Calibre LVS
• Extracting and simulating with parasitic data