I/O Designer
Categories: Expedition, PADS
This course teaches you how to manage the data and monitor the changes between the two design flows while maintaining consistency. View course highlights ↓
Scheduled classes
| Date | Location | Time | Language | Price | |
|---|---|---|---|---|---|
| Jun 25–26 | Munich | 9–5 PM CEST |
German | 1,300 EUR | Register |
| Jul 9–10 | Newbury | 9–5 PM BST |
English | 900 GBP | Register |
| Jul 9–10 | Utrecht | 9–5 PM CEST |
English | 1,300 EUR | Register |
| Jul 10–11 | Online | 8–2 PM PDT |
English | 1,400 USD | Register |
| Nov 12–14 | Online | 8–2 PM PST |
English | 1,400 USD | Register |
| Dec 4–5 | Munich | 9–5 PM CET |
German | 1,300 EUR | Register |
| Don't see the class you need? Request a class | |||||
Course Highlights
You will learn how to
- Use I/O Designer in different design scenarios
- Create an I/O Designer database
- Assign signals read in from a HDL file to the FPGA device pins
- Automatically unravel signals and buses based on the PCB floorplan
- Create symbols using different fracturing schemes
- Export the created symbols to a schematic tool
- Update and synchronize the changes between the two design flows
- Use I/O Designer to optimize Multi-FPGA Designs
- Manage the database in a team design using version control mechanisms
Hands-on labs
- I/O Designer GUI and software configuration
- Setup of FPGA/PCB projects in various design environments and design styles
- Defining the FPGA I/O design either in I/O Designer or the FPGA flow or the PCB flow
- Generation of the schematic sheets and symbols and the FPGA PCB mapping data
- Update and synchronize changes between the two design flows
- Use I/O Designer to optimize Multi-FPGA Designs
- Manage the database in a team design using version control mechanisms
Course Details
| Prerequisites |
A general understanding of PCB and FPGA design flows Knowledge of schematic capture and PCB layout |
| Course Part Number |
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| Products Covered | |
| Guides |