ModelSim / Questa Core: Advanced Topics
Categories: Questa & ModelSim
ModelSim® / Questa® Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim / Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence of simulation thoroughness and completeness. View course highlights ↓
Scheduled classes
| Date | Location | Time | Language | Price | |
|---|---|---|---|---|---|
| Jun 18–19 | Meudon | 9–5 PM CEST |
French | 1,300 EUR | Register |
| Jul 10–12 | Online | 8–2 PM PDT |
English | 1,400 USD | Register |
| Jul 17–18 | Dallas | 9–5 PM CDT |
English | 1,400 USD | Register |
| Jul 23–24 | Herzliya | 5–5 PM IDT |
English | 4,048 ILS | Register |
| Sep 18–19 | Fremont | 9–5 PM PDT |
English | 1,400 USD | Register |
| Oct 1–3 | Online | 8–2 PM PDT |
English | 1,400 USD | Register |
| Don't see the class you need? Request a class | |||||
Course Highlights
You will learn how to
- Use advanced debugging concepts and methods
- Address advanced design topics and issues
- Take advantage of advanced cross-window capabilities supporting debugging
- Manipulate designs and the ModelSim environment using Tcl/Tk
- Customize design monitors and comparators using Tcl/Tk
- Determine design "Code Coverage" for verification scenarios
- Use ModelSim in debug and performance modes
- Use the Memory and Statistical profiler to find bottlenecks in your code
- Use "Virtual Objects" to explore designs under test
- Perform advanced design probing with "Signal Spy"
- Create and compare multiple data sets
- Use advanced waveform comparison features
- Visualize and debug Finite State Macines with the FSM Viewer
- Use ModelSim for simulating Verilog, SystemVerilog, SystemC, and VHDL designs
- Analyze and improve design and end product performance from high level abstract design description through gate level implementations
- Debug multiple types of specific design errors
Hands-on labs
- Simulating using Tcl commands and a Tcl script
- Using Tcl/Tk to customize ModelSim / Questa Core
- Simulating with Code Coverage and analyzing results
- Using ModelSim in debug and performance modes
- Using the statistical profiler to analyze testbench and design bottlenecks
- Mixed-HDL design probing using Signal Spy
- Waveform comparison
- Perform gate-level timing simulations
- Perform Verilog PLI and SystemVerilog DPI simulations
- Perform causality traceback
- Debugging iteration limit errors
- Debugging logic errors
- Debugging logical unknown X values using the Dataflow window
Key topics
- Introduction to functional verification
- ModelSim / Questa Core customization with Tcl/Tk
- Code Coverage analysis
- vopt (performance) mode versus debug mode
- Optimization flows and methods
- Statistical Performance analysis
- Virtual Objects and Signal Spy
- Viewing multiple datasets
- Waveform comparison
- HDL support and gate-level simulation
- FSM Viewer
- Event Tracing
- Selected advanced design debugging techniques using various ModelSim windows
Hear from an instructor why you should sign up for this class. View Video
Course Details
| Prerequisites |
The student should have VHDL or Verilog knowledge prior to attending this course. The student should have beginner ModelSim / Questa Core skills prior to attending this course, or take the ModelSim / Questa Core: HDL Simulation class. |
| Course Part Number |
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| Products Covered | |
| Guides |
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