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ModelSim / Questa Core: HDL Simulation

Categories: FPGA, HDL & Other Languages, Questa & ModelSim

ModelSim / Questa Core: HDL Simulation teaches you to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. View course details ↓


Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Apr 12015 Bangalore India 9:30–5:30 PM
English 19,710 INR Register
Apr 212015 Tokyo Japan 10–5 PM
Japanese 50,000 JPY Register
Aug 52015 Bangalore India 9:30–5:30 PM
English 19,710 INR Register
Nov 42015 Bangalore India 9:30–5:30 PM
English 19,710 INR Register
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Course Highlights

You will learn how to

  • Invoke the ModelSim / Questa Core program
  • Prepare VHDL and Verilog data for use by ModelSim / Questa Core
  • Create and use design Libraries
  • Use ModelSim / Questa Core commands to run a simulation
  • Create a simple simulation script
  • Use ModelSim / Questa Core for batch simulations
  • Use the ModelSim / Questa Core Graphical User Interface
  • Create a ModelSim / Questa Core project
  • Simulate VHDL or Verilog designs
  • Simulate mixed VHDL/Verilog designs

Hands-on labs

  • ModelSim / Questa Core Graphic User Interface
  • Invoke and use basic simulation commands
  • Create a basic simulation script
  • Create data libraries and simulate VHDL and Verilog designs
  • Detect Verilog hazards
  • Create a VHDL project
  • Detect and fix an error in a VHDL design
  • Create and simulate a mixed VHDL/Verilog design

Key topics

  • ModelSim / Questa Core User Inferface windows
  • Shell commands
  • Steps to invoke a design using ModelSim / Questa Core commands
  • Steps to invoke a design using the Graphic User Interface
  • The advantages of using projects
  • Libraries in the ModelSim / Questa Core environment
  • Create and simulate mixed VHDL / Verilog HDL designs
  • Design hierarchy / building and simulating Designs
  • Verilog hazards

Course Information


Some VHDL or Verilog knowledge

Some familiarity with digital design concepts

Course Part Number
  • Classroom: 202339
  • Live online: 239711

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