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Olympus-SoC

Categories: Olympus-SoC

This course introduces the Olympus-SoCĀ® Place & Route tool to designers already familiar with IC chip design. View course highlights ↓

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Course Overview

It is targeted to those designers working at smaller process nodes, and who need to design and optimize for multiple corners across multiple modes. Students will experience first hand how this fully automated netlist to GDSII physical implementation system can implement complex designs at the latest process nodes. Students will be exposed to all the stages of the backend flow including pre-CTS optimization, CTS, post-CTS optimization and routing. When finished with this course, students will know how to use the built-in configurable flow options to design and optimize layouts before, during and after clock tree synthesis in a fraction of the time it would take using other tools.

Taught by industry experts and filled with dozens of examples, real-life labs, and applications, this course provides theory and concepts, tips and best practices, and hands-on experience. This all adds up to a true competitive edge.

You will learn how to

  • Set up for multi-corner, multi-mode (MCMM) optimization
  • Understand how and why to use MCMM optimization for each stage of the netlist to GDS flow
  • Learn how to access the in memory data model using a Tcl interface
  • Use the built-in Flow Kit to take a design from floorplan to post-route (fully placed, routed, and optimized)
  • Configure the Flow Kit to fit your specific design needs
  • Write out design data in .db, session, and GDSII formats
  • Perform basic chip finishing and DFM tasks using Olympus-SoC

Hands-on labs

  • Customizing the Olympus-SoC user interface
  • Inspecting library, technology, and design data
  • Defining modes and corners
  • Writing and running an Olympus-SoC script
  • Running the following flows:
    • RC optimization
    • Pre-CTS
    • CTS
    • Post-CTS
    • Route
    • Post-Route
  • Optimizing for setup, hold, area recovery, power recovery, maxtrans
  • Optimizing for signal integrity
  • Saving design data in GDSII format

Course Details

Prerequisites

Knowledge of chip design concepts and tools

Familiarity with UNIX/Linux

Experience writing and/or running Tcl scripts for place and route tools

Course Part Number
  • Instructor-led: 242761
Products Covered
  • None
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