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OVM to UVM Transition

Categories: HDL & Other Languages, SystemVerilog

This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and changed features of UVM from OVM. View course highlights ↓

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Course Highlights

You will learn how to

  • Use the features in UVM that are new or changed from OVM.

Hands-on labs

  • Throughout this course, extensive hands-on lab exercises provide you with practical experience using Questa software and the UVM library.

Course Details

Prerequisites

SystemVerilog OVM training course or equivalent SystemVerilog & OVM experience.

Course Part Number
  • Instructor-led: 248468
  • Live online: 248469
Products Covered
  • None

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