OVM to UVM Transition
Categories: HDL & Other Languages, SystemVerilog
This course is for engineers who are familiar with the Open Verification Methodology (OVM) and would like to learn testbench development with the Universal Verification Methodology (UVM). Covered are the new and changed features of UVM from OVM. View course highlights ↓
Scheduled classes
| Date | Location | Time | Language | Price | |
|---|---|---|---|---|---|
| Jun 5–6 | Meudon | 9–5 PM CEST |
French | 1,300 EUR | Register |
| Jul 15–16 | Fremont | 9–5 PM PDT |
English | 1,400 USD | Register |
| Aug 26–28 | Singapore | 9–5 PM SGT |
English | 2,000 USD | Register |
| Sep 15–16 | Herzliya | 9–5 PM IST |
English | 4,048 ILS | Register |
| Nov 21–22 | Fremont | 9–5 PM PST |
English | 1,400 USD | Register |
| Dec 2–3 | Bangalore | 9:30–5:30 PM SGT |
English | 34,500 INR | Register |
| Jan 7–8 | Austin | 9–5 PM CST |
English | 1,400 USD | Register |
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Course Highlights
You will learn how to
- Use the features in UVM that are new or changed from OVM.
Hands-on labs
- Throughout this course, extensive hands-on lab exercises provide you with practical experience using Questa software and the UVM library.
Course Details
| Prerequisites |
SystemVerilog OVM training course or equivalent SystemVerilog & OVM experience. |
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| Products Covered |
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