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PSL: Assertion Based Verification with Questa

Categories: HDL & Other Languages, Questa & ModelSim

This class introduces you to the concept of Assertion Based Verification (ABV), and gives you the tools to start using the techniques in your design and verification tasks. The class introduces the PSL language, Accellera Version 1.1, so that you can write the properties and assertions for your code, and also considers simulating with the assertions using Questa and its assertion capabilities. It shows how Questa's assertion capabilities combine with its other aspects to help you debug your design efficiently. You will also be introduced to the Assertion Thread Viewer, and its use in debugging assertion issues. View course details ↓

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Course Highlights

The course explores Functional Coverage: what it is, why it is needed, and how the PSL cover directive can be used when measuring it. This will be shown practically using the Functional Coverage capabilities in Questa. The changes made in the language with the IEEE 1850 release are briefly reviewed.

You will learn how to

  • Apply the process of assertion based verification
  • Use the PSL Language including:
    • PSL Layers
    • PSL Flavors
    • Boolean Expressions and operators
    • Sequences (SEREs) and operators
    • Properties, and property operators
    • Directives
    • V units
    • Some Coding Guidelines
  • Compile PSL in Questa
  • Simulate with PSL in Questa including:
    • Use of the Assertion Window
  • Use of the Assertion Thread Viewer
    • Assertion Commands
    • Debugging with assertions, using other Questa Windows
  • Measure Functional Coverage:
    • The PSL Cover Directive
    • Questa Functional Coverage Windows and commands

Hands-on labs

  • Write assertions to verify basic operation of a design.
  • Use Questa to simulate and debug the assertions written in the previous lab
  • Write and debug more complex assertions, and use them to verify a design
  • Identify cover points, instrument a design for coverage and simulate it.

Course Information

Prerequisites

Basic knowledge of FPGA/ASIC design techniques and procedures

Basic knowledge of VHDL or Verilog

Experience using the Questa simulator for traditional HDL dynamic simulation.

Course Part Number
  • Classroom: 220913
  • Live online: 241643
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