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Questa ADMS for A/MS Design Verification

Categories: Questa ADMS

This course will help you acquire the skills needed to maximize your usage of Questa® ADMS™ and realize its full impact on your analog/mixed signal designs. You will study design flows and representations, in particular top-down design and bottom-up verification and how Questa ADMS may be used to bring a design to completion. View course highlights ↓

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Course Highlights

This course will help you acquire the skills needed to maximize your usage of Questa® ADMS™ and realize its full impact on your analog/mixed signal designs. You will study design flows and representations, in particular top-down design and bottom-up verification, and how Questa ADMS may be used to bring a design to completion. You will learn in detail—starting from the bases of the tools, compiling models written in any language, and running simulations—how to run effective mixed-signal simulations for both digital-centric and analog-centric flows. This will allow you to verify your full design with sensitive analog parts described at the transistor level.

Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors.

You will learn how to

  • Use Questa ADMS proficiently on large analog/mixed signal designs
  • Compile text models written in VHDL, VHDL-AMS, Verilog and Verilog-AMS
  • Set up, run, and interpret results
  • Instantiate SPICE subcircuits in an HDL design (HDL on top methodology)
  • Instantiate HDL models in a SPICE description (SPICE on top methodology)
  • Appropriately insert and configure boundary converters between analog and digital parts of your design
  • Make effective use of advanced features and tips specific to your design methodology
    • Reference hierarchical objects
    • Spy analog and digital objects
    • Save/restart & checkpoint/restore
    • Tune and debug your simulation
    • Unified Coverage DataBase
    • Analyze design or simulation issues with the Statistics File

Hands-on labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Questa ADMS software. Hands-on lab topics include:

  • Introduction to Questa ADMS
  • Managing Libraries
  • Running Simulations
  • SPICE Design Configuration
  • HDL Instantiating SPICE Designs
  • Boundary Models
  • Advanced simulation features

Course Details

Prerequisites

Knowledge of principals of SPICE simulation

Working knowledge of Hardware Description Languages (VHDL and/or Verilog)

Familiarity with Questa® is a plus

Practical experience with analog design and simulation is a plus

Course Part Number
  • Instructor-led: 217225
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