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Questa Clock Domain Crossing Verification

Categories: Questa & ModelSim

This course is for design and verification engineers that need to understand how to address the challenges asynchronous clocks pose on their verification methodology. The course will cover the methodology required to run structural analysis to pinpoint potential synchronization issues between clock domains, dynamic checking with assertions of CDC protocols, and how to perform metastability effects modeling in simulation to find intricate clock domain crossing bugs. View course details ↓


Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Mar 32015 Sesto San Giovanni (MI) Italy 9–5 PM
Italian 650 EUR Register
Mar 312015 Bangalore India 9:30–5:30 PM
English 19,710 INR Register
Aug 242015 Bangalore India 9–5 PM
English 19,710 INR Register
Nov 162015 Bangalore India 9:30–5:30 PM
English 19,710 INR Register
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You will learn how to

  • Develop a methodology for CDC verification
  • Utilize static analysis to check that synchronizers exist and are connected properly at the clock domain boundaries of a design
    • Compile and analyze Verilog and VHDL RTL designs
    • Use the graphical CDC debug environment
  • Use automatically generated assertions to check that CDC signals are being driven with the correct protocol in simulation
    • Compile and run assertions in simulation
    • Debug simulation failures
    • View CDC coverage
  • Add metastability effects modeling to your simulation
    • Debug simulation failures
    • View metastability effects coverage

Hands-on Labs

  • Static analysis and debug
  • Protocol checking with assertions
  • Metastability effects modeling in simulation
  • Coverage

Key Topics

  • Introduction to Clock Domain Crossing Verification
  • CDC Methodology Recommendations
  • Synchronizer structures
  • Static CDC checking and debugging
  • CDC Protocol checking and debugging
  • Metastability effects modeling and debugging
  • Coverage measurement

Course Information

Intended for

Design Engineers

Verification Engineers


Basic knowledge of VHDL or Verilog RTL design

Familiarity with HDL simulation

Course Part Number
  • Classroom: 234959

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