Questa Clock Domain Crossing Verification

Categories: Questa & ModelSim

This course is for design and verification engineers that need to understand how to address the challenges asynchronous clocks pose on their verification methodology. The course will cover the methodology required to run structural analysis to pinpoint potential synchronization issues between clock domains, dynamic checking with assertions of CDC protocols, and how to perform metastability effects modeling in simulation to find intricate clock domain crossing bugs. View course highlights ↓

Scheduled classes

There are no classes currently scheduled for this course. Request a class

You will learn how to

  • Develop a methodology for CDC verification
  • Utilize static analysis to check that synchronizers exist and are connected properly at the clock domain boundaries of a design
    • Compile and analyze Verilog and VHDL RTL designs
    • Use the graphical CDC debug environment
  • Use automatically generated assertions to check that CDC signals are being driven with the correct protocol in simulation
    • Compile and run assertions in simulation
    • Debug simulation failures
    • View CDC coverage
  • Add metastability effects modeling to your simulation
    • Debug simulation failures
    • View metastability effects coverage

Hands-on Labs

  • Static analysis and debug
  • Protocol checking with assertions
  • Metastability effects modeling in simulation
  • Coverage

Key Topics

  • Introduction to Clock Domain Crossing Verification
  • CDC Methodology Recommendations
  • Synchronizer structures
  • Static CDC checking and debugging
  • CDC Protocol checking and debugging
  • Metastability effects modeling and debugging
  • Coverage measurement

Course Details

Intended for

Design Engineers

Verification Engineers
Prerequisites

Basic knowledge of VHDL or Verilog RTL design

Familiarity with HDL simulation
Course Part Number
  • Instructor-led: 234959
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