Questa Essentials
Categories: Questa & ModelSim
This course will teach you the benefits of Questa’s advanced verification environment. Lectures include advanced functional verification topics such as constrained-random stimulus generation, functional coverage, code coverage, and SystemVerilog assertions. View course highlights ↓
Scheduled classes
| Date | Location | Time | Language | Price | |
|---|---|---|---|---|---|
| Nov 18–19 | Herzliya | 9–5 PM IST |
English | 4,048 ILS | Register |
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Course Highlights
You will learn how to
- Create a Verification Plan
- Perform “Code Coverage” on a design
- Debug SystemVerilog Assertions in the GUI
- Create constrained random simulation environments
- Debug conflicting constraints
- Create and save different verification runs in the UCDB
- View covergroups, assertions, and cover directives in the GUI
- Debug SystemVerilog Assertions in the Assertion Thread Viewer (ATV)
- Import a test plan into the Verification Management Test Browser
- View and track the Test Plan and regression tests in the Test Tracker window
- Merge regressions tests and rank them
- Find and fix unlinked test items in the Verification Plan
- Experiment with Questa’s advanced debugging capabilities
- Call a “C” function from SystemVerilog through DPI
- Use Questa’s Power Aware functionality using UPF
- Use commands to facilitate performance and debugging
- Create and record Verilog and SystemVerilog transactions
- View transactions in the GUI
Hands-on labs
- The Verification Plan
- Code Coverage
- Debugging SystemVerilog Assertions
- Debugging a failure in the constraint solver
- Verification Management highlighting OVM methodology
- Debugging
- DPI
- Power Aware using UPF
- Vopt and performance
- Transactions
Course Details
| Prerequisites |
Familiarity with SystemVerilog class-based objects, constrained random, functional coverage, and assertions Familiarity with VHDL and Verilog |
| Course Part Number |
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| Products Covered | |
| Guides |