Sign In
Forgot Password?
Sign In | | Create Account

Signal Integrity and High Speed Methodology

Categories: Expedition/Xpedition, HyperLynx

Learn the methodology, techniques and processes that have enabled the world's foremost electronic design companies to pioneer leading edge designs. Signal integrity and high-speed methodology will teach you to make quality digital designs and printed circuit boards through knowledge of signal integrity. View course details ↓


Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Apr 13–152015 Munich Germany 9–5 PM
German 1,950 EUR Register
Don't see the class you need? Request a class

Course Highlights

The lecture modules address transmission lines and their effects on digital circuitry and printed circuit boards. Our industry expert instructors will lead you through detailed examples from real-world designs to demonstrate the necessity of understanding signal integrity issues and applying sound signal integrity principles to your designs. Specific tools are rarely discussed and therefore the class is appropriate for all Engineers involved in high speed digital pcb designs.

You will learn how to

  • Transmission lines and their effect on digital circuitry
  • Printed circuit boards: Zo, Zdiff, stackup, plane placement, crosstalk
  • Termination, topology, timing, parasitics, etc
  • Differential pair: routing, timing, crosstalk, common mode, terminating, multi-GHz
  • Crosstalk: microstrip vs stripline, forward & reverse, timing & jitter, understanding and preventing
  • Power integrity: planes, capacitors – ESL, size, location, mounting inductance
  • Reference planes: ground, power, return currents, splits, crosstalk, stitch caps
  • Vias: reference changes, stub lengths, stackup, impedance
  • Connectors: pinouts for high speed return current & crosstalk
  • High Speed Layout: vias, connectors, capacitors, PCB losses, planes
  • S Parameters
  • Testing Issues: equipment, probes, test points
  • Models: IBIS, drivers, receivers, simulators and accuracy

Key topics

What is a transmission line?

  • What causes transmission lines
  • What do they do to digital circuitry
  • Avoiding transmission line problems

Transmission Line Effects

  • Undershoot & Overshoot – can destroy boards
  • Ringback, monotonicity, crosstalk , timing

Printed Circuit Boards

  • Stackup
  • Making controlled Zo
  • Controlled Zo or controlled distance
  • Crosstalk problems with multiple vendors

Drivers, Receivers, Zo

  • Strength & speed
  • Zo & drivers
  • Incident vs. reflected wave switching

Board Interconnect Delay

  • How it is different than system delay
  • Need to include interconnect delay in timing
  • How it is calculated
  • Receiver input C, driver output Rs, PCB Zo, etc
  • Reflected vs. incident wave switching


  • When it is necessary
  • Required to stop undershoot and overshoot
  • Placement and stub length
  • Parallel, series, Zo matching, driver Rs matching
  • Diodes – dangerous


  • When are topologies important
  • How do topologies affect signal integrity & timing
  • Short & long Tee, star, daisy chain
  • Stub length

Package Parasitic

  • L’s, C’s and R’s
  • How do they affect signal integrity & timing
  • Capacitive loading on transmission lines

Differential Pair

  • Why are they important
  • Noise and EMI
  • Layout issues
  • Zdiff, Zcomm, Zeven, & Zodd
  • Controlling Zdiff
  • Side to side vs broadside (over/under)
  • Weak vs strong coupling
  • Zdiff problems
  • Skew affects on signal integrity & timing
  • Better terminations
  • How to make differential pair for > 3 GHz


  • What causes crosstalk
  • Routing densities
  • Effects on timing & signal integrity
  • Microstrip vs stripline are different
  • Same layer vs dual stripline over/under
  • Differential pair crosstalk
  • Fixing crosstalk
  • What needs to be done by layout engineers

Groundbounce – SSN

  • What causes groundbounce
  • What does it do to driver & receiver voltage levels
  • Problems with FPGA’s and ASIC’s

PCB Power Integrity

  • Planes
    • Power & ground
    • Spacing & location – loop inductance
  • Bypass Capacitors
    • ESL
    • Package & size uf
    • Spacing to load
    • Location on PCB & empty spaces
    • Mounting inductance, via placement, spacing, pads etc

Reference Planes

  • Perforation
  • Crossing splits
  • Reference consistency in designs
  • Vias, layer changes & references
  • Controls routing & stackup


  • Controlled Zo, geometry, pinouts
  • Reference consistency
  • Coupling
  • How many grounds & Vccs – return currents


  • Zo changes
  • Reference changes
  • Stub lengths
  • Blind & buried vias
  • Pads, antipads, hold diameter
  • How to make a 10 GHz via

AC Losses

  • Skin effect & dielectric loss
  • Microstrip vs stripline
  • Noise margins with differential pair
  • Pre-emphasis & equalization

Layout Issues

  • Boards are becoming more difficult to layout
  • What issues are important in today’s fast boards for layout
  • PCB’s are now part of the design

Testing Issues

  • Faster boards are harder to test
  • How do you test them
  • What equipment do you need
  • How fast does the equipment need to be

S Parameters

  • Frequency dependent descriptors
  • Good for gigahertz designs
  • S21 – Insertion loss or interconnect loss for SI
  • Includes discontinuities, connectors, packages
  • VNA – 2 & 4 port networks

IBIS Models

  • Drivers & receivers
  • Simulators
  • Accuracy
  • Repairing and modifying

Quality Board Designs

  • How to make quality boards
  • What tools are needed
  • Signal integrity issues must be included

Course Information

Prerequisites None
Course Part Number
  • Classroom: 207339
Online Chat