Sign In
Forgot Password?
Sign In | | Create Account

Signal Integrity & EMC Process

Categories: Expedition/Xpedition, HyperLynx

This is a class about how to move from a trial and error process to a proven "right the first time" methodology. You will add about 4 days effort per design, but will save an average of 2 board turns at 4 weeks per turn. View course details ↓


Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Mar 18–202015 Singapore Singapore 9:30–5:30 PM
English 2,000 USD Register
Don't see the class you need? Request a class

Course Highlights

The pinnacle achievement for most Engineers, and Layout Designers is to design a system that works reliably at full speed and is still quiet enough to pass FCC and CISPR tests without expensive shielding and filtering... and to do it on the first try.

You will learn how to

  • Implement a solid high speed system design process
    • Produce a solid, reliable, quiet system on the first board implementation
    • Save an average of 2 board spins per design
    • Give the software developers a reliable test bed that works at full speed
    • Allow engineers, layout designers, and managers to operate more efficiently

Hands-on Lab

Lab exercises provide practical experience to solidify the concepts. This course will have the students stepping through a methodology for "right the first time" design and layout.

Key topics

  • The Holistic Nature of Signal Integrity, Radiated Emissions, and Susceptibility
  • Board Stack-up... What is a good or bad stack-up and why?
  • Power Integrity... In adequate capacitance > ground bounce > SI errors & Radiated Emissions
  • High Speed Routing Rules, Via Placement, and Return Current Control
  • Termination Schemes and their Ramifications
  • Cross Talk ... how to predict it and how to control it
  • LVDS and SERDES ... how these pseudo- differential signals really work
  • Radiated Emissions... What causes FCC & CISPR radiated emission failure?
  • Analogue / Digital interface - isolation
  • Signal Triage, Noise Budgeting and Planning for Success
  • The Jump Start Process... putting the pieces together for a "right the first time" design
  • Class Design Lab using the Jump Start Process
  • Pre-layout Design Review
  • Post Layout Design Review
  • Going off board...connectors, back planes, cables, and how you can avoid really big problems
  • Susceptibility... How to "bullet proof" your design.

Course Information

Intended for

The class is for engineers and layout designers who need to implement a high speed system design process in their organization, whether jumpstarting a new design or fixing previous designs.


Experience with PCB design, layout or manufacturing

S.I. and EMC experience is helpful but not required

Course Part Number
  • Classroom: 237765

Recently viewed courses

Online Chat