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SystemC Advanced Verification

Categories: HDL & Other Languages, SystemC

This intensive, practical course is intended for engineers familiar with SystemC who have an interest in learning about the SystemC Verification Library (SCV) and verification techniques using the library. View course highlights ↓

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Course Highlights

You will learn how to

  • Approach functional verification using C++ and the SystemC SCV Library
  • Structure an object-oriented, configurable and reusable verification environment
  • Generate and apply constrained random stimulus
  • Perform mixed-language verification of VHDL and Verilog modules
  • Apply Transaction-based verification techniques
  • Apply the C++ Standard Template Library (STL) to assist verification
  • Create a reactive verification system which observes & tracks design response to automatically modify test activity

Hands-on labs

  • Using STL containers and algorithms
  • Transaction-based stimulus and response recording
  • Co-simulate with RTL components
  • Randomizing control flow
  • Creating and synchronizing dynamic concurrent processes
  • Constraint-driven stimulus with reactive feedback

Course Details

Intended for
Modeling Engineers interested in SystemC for System Verification
Strong familiarity with C++
Familiarity with SystemC
Prerequisites None
Course Part Number
  • Instructor-led: 227425
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