The Tessent IJTAG course drives the development of your skills and knowledge using Instrument Connectivity Language (ICL) in order to describe the interfaces and connectivity in your design View course details ↓
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Designing a modern product requires the integration of multiple IP block from both in-house and third party sources. The Mentor Graphics Tessent® IJTAG solution delivers comprehensive automation support for implementing the IEEE P1687 standard, providing plug-and-play IP test and instrumentation integration.
The Tessent® IJTAG course drives the development of your skills and knowledge using Instrument Connectivity Language (ICL) in order to describe the interfaces and connectivity in your design. It also teaches you how to use the Procedure Description Language (PDL) in order to define operations applied to individual IP blocks. This course teaches you to extract the IJTAG ICL network data from the gate-level or RTL netlist; then uses these extracted networks to retarget PDL commands from the IP boundary to any point within an ICL-described IEEE P1687 Network.
The chip-level PDL commands can be translated to ATE pattern formats (STIL, WGL, and so on). ModelSim® is used to generate Verilog testbenches for these PDL verifications in some of the labs.
The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with Mentor Graphics Tessent IJTAG and Tessent TestKompress tools under the guidance of industry-expert instructors.
You will learn how to
- Describe the motivation for IEEE P1687.
- List core aspects and functionality of IEEE P1687:
- Instrument Connectivity Language (ICL).
- Procedure Description Language (PDL).
- Explain how IEEE P1687 extends the use of IEEE 1149.1 and IEEE 1500.
- Perform ICL Network Extraction and PDL Command Retargeting flows.
- Describe instruments using ICL and its advanced features to manipulate data in your design (alias, parameter, enumeration table).
- Leverage IEEE 1149.1/IEEE 1500-based test access architecture to perform IJTAG.
- Use Tessent® IJTAG DRC syntax and semantics rules to debug your design using DFTVisualizer.
- Implement and use Tessent® IJTAG in TestKompress (configure EDT IPs and another embedded IJTAG instruments needed for scan ATPG.
- Construct the primitive ICL instrument.
- Connect the component ICL instances to build a top level ICL netlist.
- Invoke Tessent IJTAG in Tessent Shell.
- List basic steps in the IJTAG retargeting flow.
- Use basic commands in order to gain access to an ICL instrument.
- Create and write out different retargeting command sets.
- Use advance syntaxes and features of ICL.
- Explain how to use IJTAG introspection.
- Write a PDL procedure to gain access to the instrument.
- Describe tool behavior when creating retargeting PDL commands.
- Create PDL commands.
- Verify created retargeting PDL commands.
- Incorporate IEEE 1149.1 into your design.
- Create and implement a multi-TAP configuration
- Create retargeted PDL command.
- Shift data through the ICL network in order to access the instrument.
- Create a testbench for retargeting PDL command.
- Do a basic ICL network extraction flow.
- Extract the network from bottom-up or top-down.
- Understand how the tool matches the module in the netlist with the available ICL module.
- Use the extracted ICL network to create retargeting PDL command file.
- Incorporate an IJTAG design into the Tessent TestKompress flow.
- Use PDL for ATPG setup and chain test.
- Use iCall in the test_setup/test_end procedure for ATPG pattern generation.
Diagnosis/failure analysis engineers
A intermediate background in DFT
Some knowledge of TCL is helpful
Some knowledge about IEEE 1149.1 is helpful
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