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Tessent MemoryBIST and LogicBIST

Categories: Tessent

This course will help you understand how to implement DFT for memory and logic test. You will be introduced to Tessentâ„¢ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit. View course details ↓


Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Sep 28–302014 Herzliya Israel 9–5 PM
English 6,999 ILS Register
Oct 7–92014 El Segundo California 9–5 PM
English 2,400 USD Register
Oct 15–172014 Bangalore India 9:30–5:30 PM
English 59,130 INR Register
Dec 10–122014 Singapore Singapore 9–5 PM
English 2,000 USD Register
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Course Highlights

You will learn how to

  • Perform DFT design rule checking on a chip design for embedded memory test
  • Generate, insert, and verify Tessent MemoryBIST IP in a design
  • Perform DFT design rule checking on a chip design for embedded digital logic test
  • Generate, insert, and verify Tessent LogicBIST IP in a hierarchical logic cores
  • Generate, insert, and verify scan chains in hierarchical logic cores
  • Analyze fault coverage and insert test points to increase fault coverage
  • Perform DFT design rule checking on a chip design for TAP and boundary scan test
  • Generate, insert, and verify the TAP and boundary-scan logic at the chip level

Hands-on labs

  • Demonstrate the flow for Tessent Boundary Scan, and Tessent MemoryBIST
  • Demonstrate the above flow with the addition of Tessent LogicBIST
  • Both labs focus on the flow and give you an example of some basic features of the Tessent IP
  • The labs serve as a template for use when implementing DFT on a user design

Course Information


2 years experience in ASIC design using RTL

2 years experience using DFT tools for scan insertion and ATPG

Basic understanding of DFT flows and DFT methodology

Experience with HDL-based logic synthesis

Experience with UNIX directories and editing text files (for lab exercises)

Course Part Number
  • Classroom: 241169
  • Live online: 247988

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