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Tessent MemoryBIST and LogicBIST

Categories: Tessent

The Tessent® Memory BIST and Logic BIST course will help you understand how to implement DFT for memory and logic test. You will be introduced to Tessent technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. View course details ↓

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Date Time Language Price
Jan 12–152015 8–2 PM
PST
English 2,400 USD Register

Classroom

Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Jan 19–212015 Bangalore India 9:30–5:30 PM
IST
English 59,130 INR Register
Feb 16–182015 Herzliya Israel 9–5 PM
IST
English 6,999 ILS Register
Mar 16–182015 Singapore Singapore 9–5 PM
SGT
English 2,000 USD Register
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Course Details

The Tessent® Memory BIST and Logic BIST course will help you understand how to implement DFT for memory and logic test. You will be introduced to Tessent technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit.

Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors.

You will learn how to

  • Perform DFT design rule checking on a chip design for embedded memory test
  • Generate, insert, and verify Tessent MemoryBIST IP in a design
  • Perform DFT design rule checking on a chip design for embedded digital logic test
  • Troubleshoot common problems: blocked clocks, clock gaters, tool limitations with language constructs
  • Define an alternative clock for BIST • Use properties to sensitize clock paths through muxes and clock gating cells
  • Use custom algorithms and user-defined sequences to limit runs to specific controllers, if programmable
  • Use custom algorithms to define initialization sequences during start up, like that used to initialize a PLL
  • Generate, insert, and verify Tessent LogicBIST IP in a hierarchical logic cores
  • Generate, insert, and verify scan chains in hierarchical logic cores
  • Analyze fault coverage and insert test points to increase fault coverage
  • Perform DFT design rule checking on a chip design for TAP and boundary scan test
  • Generate, insert, and verify the TAP and boundary-scan logic at the chip level
  • Perform basic memory analysis and repair

Hands-on labs

  • Demonstrate the flow for Tessent Boundary Scan, and Tessent MemoryBIST
  • Demonstrate the above flow with the addition of Tessent LogicBIST
  • Labs focus on the flow and give you an example of some basic features of the Tessent IP
  • The labs serve as a template for use when implementing DFT on a user-generated design

Course Information

Prerequisites

2 years experience in ASIC design using RTL

2 years experience using DFT tools for scan insertion and ATPG

Basic understanding of DFT flows and DFT methodology

Experience with HDL-based logic synthesis

Experience with UNIX directories and editing text files (for lab exercises)

Course Part Number
  • Classroom: 241169
  • Live online: 247988
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