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Tessent MemoryBIST and LogicBIST

Categories: Tessent

This course will help you understand how to implement DFT for memory and logic test. You will be introduced to Tessentâ„¢ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit. View course details ↓

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Course Highlights

You will learn how to

  • Perform DFT design rule checking on a chip design for embedded memory test
  • Generate, insert, and verify Tessent MemoryBIST IP in a design
  • Perform DFT design rule checking on a chip design for embedded digital logic test
  • Generate, insert, and verify Tessent LogicBIST IP in a hierarchical logic cores
  • Generate, insert, and verify scan chains in hierarchical logic cores
  • Analyze fault coverage and insert test points to increase fault coverage
  • Perform DFT design rule checking on a chip design for TAP and boundary scan test
  • Generate, insert, and verify the TAP and boundary-scan logic at the chip level

Hands-on labs

  • Demonstrate the flow for Tessent Boundary Scan, and Tessent MemoryBIST
  • Demonstrate the above flow with the addition of Tessent LogicBIST
  • Both labs focus on the flow and give you an example of some basic features of the Tessent IP
  • The labs serve as a template for use when implementing DFT on a user design

Course Information


2 years experience in ASIC design using RTL

2 years experience using DFT tools for scan insertion and ATPG

Basic understanding of DFT flows and DFT methodology

Experience with HDL-based logic synthesis

Experience with UNIX directories and editing text files (for lab exercises)

Course Part Number
  • Classroom: 241169
  • Live online: 247988

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