Tessent MemoryBIST
Categories: Tessent
This course will help you understand how to implement DFT for memory test. You will be introduced to Tessent™ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit. View course highlights ↓
Scheduled classes
| Date | Location | Time | Language | Price | |
|---|---|---|---|---|---|
| Jun 12–13 | Hsinchu City | 9:30–5:30 PM CST |
Mandarin | 22,000 TWD | Register |
| Jun 16–17 | Herzliya | 9–5 PM IDT |
English | 4,666 ILS | Register |
| Don't see the class you need? Request a class | |||||
Course Highlights
You will learn how to
- Perform DFT design rule checking on a chip design for embedded memory test using the Tessent MemoryBIST flow
- Generate, insert, and verify Tessent MemoryBIST IP in a design
- Perform DFT design rule checking on a chip design for TAP and boundary scan test
- Generate, insert, and verify the TAP and boundary-scan logic at the chip level
- Perform basic memory analysis and repair
Hands-on labs
- Demonstrate the flow for Tessent Boundary Scan, and Tessent MemoryBIST
- Labs focus on the flow and give you an example of some basic features of the Tessent IP
- The labs serve as a template for use when implementing DFT on a user-generated design
Course Details
| Prerequisites |
2 years experience in ASIC design using RTL 2 years experience using DFT tools for scan insertion and ATPG Basic understanding of DFT flows and DFT methodology Experience with HDL-based logic synthesis Experience with UNIX directories and editing text files (for lab exercises) |
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