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Tessent MemoryBIST

Categories: Tessent

This course will help you understand how to implement DFT for memory test. You will be introduced to Tessentâ„¢ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit. View course highlights ↓

Online

Our instructor-led online classes offer all the benefits of classroom training without the travel. Participate in a live classroom experience, complete with hands-on exercises and course materials, directly from your office.

Date Time Language Price
Jun 3–52014 8–2 PM
PDT
English 1,600 USD Register

Classroom

Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
May 6–72014 Hsinchu City Taiwan 9:30–5:30 PM
CST
Mandarin 22,000 TWD Register
Jun 23–242014 Austin Texas 9–5 PM
CDT
English 1,600 USD Register
Jul 21–222014 El Segundo California 9–5:20 PM
PDT
English 1,600 USD Register
Sep 8–92014 Tempe Arizona 9–5 PM
MST
English 1,600 USD Register
Nov 17–182014 Fremont California 9–5 PM
PST
English 1,600 USD Register
Jan 13–142015 Austin Texas 9–5 PM
CST
English 1,600 USD Register
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Course Highlights

You will learn how to

  • Perform DFT design rule checking on a chip design for embedded memory test using the Tessent MemoryBIST flow
  • Generate, insert, and verify Tessent MemoryBIST IP in a design 
  • Perform DFT design rule checking on a chip design for TAP and boundary scan test
  • Generate, insert, and verify the TAP and boundary-scan logic at the chip level
  • Perform basic memory analysis and repair

Hands-on labs

  • Demonstrate the flow for Tessent Boundary Scan, and Tessent MemoryBIST
  • Labs focus on the flow and give you an example of some basic features of the Tessent IP
  • The labs serve as a template for use when implementing DFT on a user-generated design

Course Details

Prerequisites

2 years experience in ASIC design using RTL

2 years experience using DFT tools for scan insertion and ATPG

Basic understanding of DFT flows and DFT methodology

Experience with HDL-based logic synthesis

Experience with UNIX directories and editing text files (for lab exercises)

Course Part Number
  • Instructor-led: 241167
  • Live online: 247987
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