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Tessent MemoryBIST

Categories: Tessent

The Tessent® MemoryBIST course will help you understand how to implement DFT for memory test. You will be introduced to Tessent™ technology and automation tools, building upon a recommended flow that a hardware engineer adding Built-In Self-Test (BIST) should follow. View course details ↓

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Course Details

The lecture/lab format of the class gives you a conceptual understanding of how BIST circuitry for random logic and memories can be automatically generated and inserted into a circuit.

Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors.

You will learn how to

  • Perform DFT design rule checking on a chip design for embedded memory test using the Tessent MemoryBIST flow
  • Generate, insert, and verify Tessent MemoryBIST IP in a design
  • Perform DFT design rule checking on a chip design for TAP and boundary scan test
  • Troubleshoot common problems: blocked clocks, clock gaters, tool limitations with language constructs
  • Define an alternative clock for BIST
  • Use properties to sensitize clock paths through muxes and clock gating cells
  • Use custom algorithms and user-defined sequences to limit runs to specific controllers, if programmable
  • Use custom algorithms to define initialization sequences during start up, like that used to initialize a PLL
  • Generate, insert, and verify the TAP and boundary-scan logic at the chip level
  • Perform basic memory analysis and repair

Hands-on labs

  • Demonstrate the flow for Tessent Boundary Scan, and Tessent MemoryBIST
  • Labs focus on the flow and give you an example of some basic features of the Tessent IP
  • The labs serve as a template for use when implementing DFT on a user-generated design

Course Information

Intended for

logic design engineers who understand IC DFT concepts (i.e., Scan-ATPG-ATE) and tools and need to understand DFT Embedded Test IP tools and DFT Embedded Test IP methodologies.

Test engineers who want to understand how Embedded Test impact their test flow.


2 years experience in ASIC design using RTL

2 years experience using DFT tools for scan insertion and ATPG

Basic understanding of DFT flows and DFT methodology

Experience with HDL-based logic synthesis

Experience with UNIX directories and editing text files (for lab exercises)

Course Part Number
  • Classroom: 241167
  • Live online: 247987

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