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Tessent Scan and ATPG

Categories: Tessent

The Tessent®: Scan and ATPG course will drive the development of your skills and knowledge in scan and ATPG design processes utilizing the Tessent Scan point tool, Tessent FastScan™, Tessent TestKompress®, and the Tessent point tool DFTVisualizer. View course highlights ↓

Online

Our instructor-led online classes offer all the benefits of classroom training without the travel. Participate in a live classroom experience, complete with hands-on exercises and course materials, directly from your office.

Date Time Language Price
Jul 8–152014 8–2 PM
PDT
English 3,200 USD Register

Classroom

Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Apr 22–252014 Fremont California 9–5 PM
PDT
English 3,200 USD Register
Apr 27–302014 Herzliya Israel 9–5 PM
IDT
English 9,332 ILS Register
May 6–92014 Bangalore India 9:30–6 PM
SGT
English 78,840 INR Register
May 13–142014 Hsinchu City Taiwan 9:30–5:30 PM
CST
Mandarin 22,000 TWD Register
May 20–232014 Tempe Arizona 9–5 PM
MST
English 3,200 USD Register
Jun 16–192014 Austin Texas 9–5 PM
CDT
English 3,200 USD Register
Jul 22–252014 Bangalore India 9:30–6 PM
SGT
English 78,840 INR Register
Aug 11–142014 El Segundo California 9–5 PM
PDT
English 3,200 USD Register
Sep 15–182014 Fremont California 9–5 PM
PDT
English 3,200 USD Register
Oct 20–232014 Tempe Arizona 9–5 PM
MST
English 3,200 USD Register
Dec 1–42014 Fremont California 9–5 PM
PST
English 3,200 USD Register
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The Tessent® Scan and ATPG course will drive the development of your skills and knowledge in scan and ATPG design utilizing the Tessent Scan, Tessent FastScan™, and the DFTVisualizer. The knowledge gained for generating test patterns in this class is directly applicable for generating test patterns for designs utilizing Tessent TestKompress. ModelSim® is used to simulate test patterns to identify potential issues (mismatches) between the expected results from pattern generation and the Verilog simulation results. During this course you will insert full scan in a design using Tessent Scan, and create high quality test patterns using the ATPG. You will also learn about ATPG compression techniques including an introduction to Tessent TestKompress.

The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with the Mentor Graphics Tessent tool suite under the guidance of industry-expert instructors.

Course Highlights

You will learn how to

  • Invoke the tessent shell environment in order to utilize Tessent Scan, Tessent FastScan, and Tessent TestKompress.
  • Setup and analyze designs to prepare for ATPG
  • Perform ATPG to achieve high test coverage with a minimal number of patterns
  • Troubleshoot DRC violations
  • Troubleshoot areas of low test coverage
  • Troubleshoot simulation mismatches

Hands-on labs

  • Accessing documentation and getting help
  • Using the scan and ATPG tool flow
  • Reading and analyzing messages
  • Troubleshooting a DRC error in DFTVisualizer
  • Using common methodologies to attain a quick estimate of test coverage
  • Troubleshooting areas of low test coverage
  • Determining the cause of undetected faults
  • Creating and saving patterns in different formats
  • Verifying patterns using ModelSim
  • Reading ASCII files into Tessent FastScan
  • Modifying timeplates
  • Creating fault models and performing fault grading

Course Details

Intended for

Designers, DFT engineers, and test consultants involved with creating testable ASICs and ICs and producing the manufacturing test sets

ATPG test engineers

CAD engineers and managers

CAD staff seeking to understand the effect of DFT on the design flow

Anyone needing a basic to intermediate level of DFT tool flow and concepts

Prerequisites

A basic background in DFT

Some knowledge of TCL is helpful

Course Part Number
  • Instructor-led: 057857
  • Live online: 239701
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