Sign In
Forgot Password?
Sign In | | Create Account

Tessent TestKompress and Advanced Topics

Categories: Tessent

This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues. View course details ↓

Classroom

Full instructor-led courses in a Mentor training facility, with complete course materials and access to classroom computers.

Date Location Time Language Price
Nov 10–112014 Bangalore India 9:30–5:30 PM
IST
English 39,420 INR Register
Nov 26–272014 Beijing China 9–5 PM
CST
Chinese (Mandarin) 5,200 CNY Register
Dec 182014 Hsinchu City Taiwan 9–5 PM
CST
Chinese (Mandarin) 300 USD Register
Jan 19–202015 Austin Texas 9–5 PM
CST
English 1,600 USD Register
Jan 22–232015 Bangalore India 9:30–5:30 PM
IST
English 39,420 INR Register
Mar 4–52015 Tempe Arizona 9–5 PM
MST
English 1,600 USD Register
Apr 16–172015 Marlborough Massachusetts 9–5 PM
EDT
English 1,600 USD Register
May 14–152015 Fremont California 9–5 PM
PDT
English 1,600 USD Register
Jul 23–242015 Austin Texas 9–5 PM
CDT
English 1,600 USD Register
Don't see the class you need? Request a class

Course Highlights

You will learn how to

  • Access help and navigate documentation for Tessent TestKompress
  • Use Tessent TestKompress in three different IP generation flows
  • Perform EDT Automation with Tessent TestKompress
  • Compare compression results
  • Create Tessent TestKompress test patterns
  • Troubleshoot common DRC violations
  • Perform At-speed testing
  • Simulate test patterns and troubleshoot mismatches
  • Use Tessent TestKompress and Boundary Scan in the same flow

Hands-on labs

  • Integrating Tessent TestKompress into Gate-level, RTL-level, and Modular Design Flows
  • Exploring Tessent TestKompress Logic Features and Options
  • Understanding and Troubleshooting Common DRC Violations
  • Determining Compression and Performance
  • Using At-speed Testing
  • Debugging Simulation Mismatches
  • Using Tessent TestKompress with Boundary Scan
  • Graphically Viewing Data and Troubleshooting Common DRCs

Course Information

Prerequisites

A background in Design-for-Test

Tessent Scan and ATPG training course

Course Part Number
  • Classroom: 221302
  • Live online: 239702
Guides
 
Online Chat