Tessent TestKompress and Advanced Topics
Categories: Tessent
This course introduces Embedded Deterministic Test (EDT™) technology and Tessent™ TestKompress® to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with smaller (< 130 nm) geometries. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size or application time are issues. View course highlights ↓
Scheduled classes
There are no classes currently scheduled for this course. Request a class
Course Highlights
You will learn how to
- Access help and navigate documentation for Tessent TestKompress
- Use Tessent TestKompress in three different IP generation flows
- Perform EDT Automation with Tessent TestKompress
- Compare compression results
- Create Tessent TestKompress test patterns
- Troubleshoot common DRC violations
- Perform At-speed testing
- Simulate test patterns and troubleshoot mismatches
- Use Tessent TestKompress and Boundary Scan in the same flow
Hands-on labs
- Integrating Tessent TestKompress into Gate-level, RTL-level, and Modular Design Flows
- Exploring Tessent TestKompress Logic Features and Options
- Understanding and Troubleshooting Common DRC Violations
- Determining Compression and Performance
- Using At-speed Testing
- Debugging Simulation Mismatches
- Using Tessent TestKompress with Boundary Scan
- Graphically Viewing Data and Troubleshooting Common DRCs
Course Details
| Prerequisites |
A background in Design-for-Test Tessent Scan and ATPG training course |
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| Products Covered | |
| Guides |