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Veloce Basic

Categories: Emulation

This course will teach basic Veloce fundamentals and help users get started with the Veloce platform details of synthesis, design mapping, bring up, options and debug and will help you get a quick start on your project. View course details ↓

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Course Highlights

Overview

Learn how to leverage examples for your specific installation. Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors.

You will learn how to

  • Setup the Veloce SW/HW environment
  • Synthesize RTL and map on Veloce
  • Implement the Veloce compile flow
  • Implement the Veloce run time flow
  • Utilize the Veloce debug flow
  • Apply Veloce basic fundamentals

Hands-on labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using the Voloce software product suite. Hands-on lab topics include the emulation of an 8051 Micro-controller.

Key Topics

  •   Product Architecture and Chassis
  • Veloce Software Compile & Run Time Flow Overview
  • Veloce Timing Specification
  • RTL compilation
  • Velsyn Compilation
  • Memories
  • Vitual Maintenance Panel For Users
  • Virtual Maintenance Panel For Administrators
  • Veloce User Interface for Debugging
  • Debussy for Debugging
  • Run Time and Visibility
  • Veloce Trigger Basics
  • Veloce Trigger Advanced

Course Information

Intended for

Verification Engineers

Design Engineers

Validation Engineers

SOC Validation Engineers
 

Prerequisites

Verilog Synthesis

Simulation Flow (Any simulator experience)

Course Part Number
  • Classroom: 256753

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