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Verilog Introduction

Categories: HDL & Other Languages, Questa & ModelSim

This course is intended for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. View course details ↓

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Course Highlights

You will learn how to

  • Avoid the common mistakes people make when first using Verilog
  • Correctly use blocking and non-blocking assignments.
  • Correctly model combinational and sequential hardware blocks
  • Write synthesizable RTL design descriptions
  • Structure and create testbenches to verify your RTL code

Hands-on labs

  • Correct usage of functions and tasks
  • How to describe bidirectional bus interfaces
  • Code a synthesizable RTL State machine

Course Information

Intended for

Design and Verification Engineers interested in Verilog

Prerequisites

Familiarity with concepts of verification

Course Part Number
  • Classroom: 230367
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