Verilog Introduction
Categories: HDL & Other Languages, Questa & ModelSim
This course is intended for designers who are new to Verilog and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. View course highlights ↓
Scheduled classes
| Date | Location | Time | Language | Price | |
|---|---|---|---|---|---|
| Jun 17–20 | Singapore | 9–5 PM SGT |
English | 2,500 USD | Register |
| Don't see the class you need? Request a class | |||||
Course Highlights
You will learn how to
- Avoid the common mistakes people make when first using Verilog
- Correctly use blocking and non-blocking assignments.
- Correctly model combinational and sequential hardware blocks
- Write synthesizable RTL design descriptions
- Structure and create testbenches to verify your RTL code
Hands-on labs
- Correct usage of functions and tasks
- How to describe bidirectional bus interfaces
- Code a synthesizable RTL State machine
Course Details
| Intended for | Design and Verification Engineers interested in Verilog |
| Prerequisites |
Familiarity with concepts of verification |
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| Products Covered | |
| Guides |