VHDL Advanced

Course Highlights

You will learn how to

• Model using a behavioral approach with VHDL’s advanced language constructs.
• Write sophisticated modern testbenches consisting of random stimulus, vector compression techniques for regressions, and basic PSL capabilities for temporal monitoring.
• Use QuestaSim’s advanced verification capabilities such as coverage, waveform comparison, and code profiling to increase your performance and test confidence.

Hands-on labs

• Write a behavioral fifo model using linked lists
• Write a reusable, parameterizable, multi-phase clock generation block
• Generate random stimulus for verification using algorithmic and LSFR methods
• Write temporal monitors for verification of bus protocols
• Write basic PSL sequences for verification
• Use advanced regression methods such as MISR’s and QuestaSim’s waveform comparison
• Using QuestaSim’s coverage and profiling tools

Key topics

• Behavioral modeling in VHDL
  • Using dynamic memory allocation for modeling
• Generating Stimulus
  • Directed stimulus with files and procedures
  • Random stimulus
  • Co-simulating with C routines
• Verifying the design
  • Assertion –based verification
  • Brief introduction to PSL
  • Regression Methods
  • Code Coverage
• Simulation Performance
• Using code profiling