VHDL-AMS 2 Day
Categories: Questa ADMS
This course will help you acquire the skills needed to write VHDL-AMS code, either modifying existing models, or developing new models to be used with Questa ADMS mixed-signal simulator. View course details ↓
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After reviewing the basics of VHDL language (optional), you will learn how to describe and manipulate analog equations, using analog dedicated objects, syntax and associated concepts. You will then discover how to write mixed-signal code, using the appropriate features of the language designed to handle digital-to-analog and analog-to-digital interactions, to perfectly handle the synchronization between the analog and digital simulation solvers.
A last section covers modeling techniques giving you guidelines to write better code when using some specific language features.
This course is mainly targeted to be delivered to users also attending a Questa ADMS class or who have a good practical experience with Questa ADMS.
You will learn how to
- How analog and mixed-signal behavioral modeling is used in mixed-signal design and verification
- The basics of VHDL (optional, only for people who are new to VHDL)
- Entity, architecture, libraries o Concurrent VHDL with signals and drivers, delays, concurrent signal assignments
- Sequential VHDL with processes, variables, wait, if and case statements
- Structural VHDL and configurations
- How VHDL has been extended to allow Analog and Mixed-Signal descriptions
- Analog language constructs
- Analog objects and branches
- Simultaneous statements
- Domains and initial conditions
- Mixed-signal language constructs
- A/D interactions
- D/A interactions
- Various mixed-signal modeling guidelines
Throughout this course, extensive hands-on lab exercises provide you with practical experience on writing VHDL-AMS models and testing them using Questa ADMS software. For those who do not have any practical experience with Questa ADMS, the basics of the tool usage will be covered, in order to perform the labs.
Analog or Digital designers
CAD designers, who want/need to develop behavioral models in VHDL-AMS or modify existing ones
Working experience with Questa ADMS, if not VHDL-AMS class to be coupled with a Questa ADMS class
Practical experience with analog design and simulation is a plus.
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