VHDL-AMS (3 Day)
Categories: HDL & Other Languages
In this class the designer will learn the basics of the VHDL-AMS (IEEE 1076.1) hardware descriptor language and its efficient use for model creation, validation, and design reuse. The class is intended for analog, mixed-signal, and mixed-nature designers who want to discover what advantages high-level modeling brings to the design process. The three days of the class are spent on the basics of the VHDL-AMS language and teaching efficient modeling practices. View course highlights ↓
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You will learn how to
This class will help designers quickly harness the potential of abstract analog and mixed-signal modeling while avoiding the problems and pitfalls of the new technology. The designer will learn the following skills:
- How to code models using the VHDL-AMS notation
- How to develop efficient mathematical models for encoding with VHDL-AMS
- How to verify and test continuous, discrete event, and mixed signal models
- How to write portable, reusable VHDL-AMS code.
Upon completion of the training class, the designer will have a good working knowledge of the VHDL-AMS language including its application to the modeling and simulation of analog, mixed-signal, and mixed-discipline circuits and systems.
Throughout this course, extensive hands-on lab exercises provide you with practical experience. Hands-on lab topics include:
- How to use the Questa ADMS tool.
- How to build analog models and simulate them in the time domain.
- How to build analog models and simulate them in the frequency domain.
- How to build mixed-signal models and simulate them in the time domain.
- How to build test benches.
- How to model and simulate mixed-nature systems.
- Understand the capabilities the language offers to model and simulate typical analog, mixed-signal, and mixed-discipline components.
- Get a global perspective of the structure of VHDL-AMS models.
- Use the Mentor Graphics Questa ADMS simulation system and discover the systems' capabilities.
- Understand what makes up a behavioral model in VHDL-AMS.
- Identify the essential language elements that are needed to describe behavior.
- The language elements are presented that describe the structure of the modeled system as well as the available mechanisms to organize a model in a hierarchical way.
- Learn the basic design units in the language that are provided to encapsulate behavior: namely the entity declaration and the architecture body.
- Learn the structural description style, that is, how to instantiate components and to interconnect them in a model.
- Learn the use of generic parameters as a way to describe flexible models; the direct instantiation method.
- Once a design is described in terms of entities, architectures, component instances, signals, processes, equations, terminals, and quantities, learn to prepare the modeled design for simulation.
- Learn to use the set of VHDL-AMS language elements that allow one to describe event-driven and continuous behavior are presented as well as more specialized language elements that allow one to build improved, more compact, behavioral models.
- A review of models for ideal linear circuit elements will be presented to see the terminal and branch quantities.
- This review will be extended to include non-ideal source models.
- From this review, some guidelines will be developed for defining branch quantities and their associated equations.
- Review the linearization process in order to understand the basis for frequency domain analysis and frequency domain noise analysis along with the VHDL-AMS language elements that support it. Start by looking at the link between time domain analysis and frequency domain analysis for linear systems.
- Given this foundation for frequency domain analysis, it will be expanded to look at what noise analysis is based on and why it is important. This will point to the need for noise sources associated with most components in the system being simulated.
- Learn how to integrate the two aspects, digital and analog, into a unified mixed-signal environment. The specialized language elements and mechanisms that support analog simulation control will be presented, namely: the definition of initial conditions to force the computation of the quiescent state of a model; the handling of discontinuities in a model with the capability to define new initial conditions for the next continuous interval; the specification of tolerances and a time step limiting scheme to control the quality of the simulation results; the definition of basic solvability checks to easily identify models that would lead to nonsolvable systems of equations.
- Learn about the power of VHDL-AMS when it comes to testing of systems, circuits and models. See creative ways to generate complex test signals with minimal effort compared to traditional analog simulators.
- See how sequences of test cases, including fault effects analysis, can be set up and run.
- Behavioral models work with the simulation engine to produce simulation results. Without a basic understanding of the simulation engine, it is possible to write models that result in excessive CPU times for simulation. One of the common errors is unwanted discontinuities in the model that can result in excessive CPU time, and/or wrong results, and/or convergence problems. Learn to write efficient models and avoid simulation run time efficiency problems.
- When doing Top-Down design of a system, lower levels of specifications become available as the design proceeds. You will be exposed to model development strategies, which map well into the Top-Down design flow.
- Many physical systems have different sets of equations depending on their operating region. Using event concepts, development of these models can be simplified. You will see the value of using events within an otherwise analog model.
- One of the major powers of VHDL-AMS is its ability to easily model and simulate systems, which span natures or model domains. Many present day high performance system designs require simultaneous tuning of parameters in different natures. VHDL-AMS allows one to do this. However, one must avoid the potential numerical problems inherent in mixed-nature models. You will learn approaches to writing efficient models for mixed-nature systems.
This course is intended for analog, digital, and mixed-signal designers who want to discover the advantages of high-level mixed-signal modeling.
VHDL Introduction or some knowledge of VHDL.
Experience with SPICE or Eldo is helpful, but not required.
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