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Visual Elite

Categories: HDL & Other Languages

The Visual Elite course covers graphical design entry for HDL, design management, simulation and debug. View course details ↓

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Course Highlights

You will learn how to

  • The Visual Elite overview
  • The graphical entry benefit
  • How to entry graphical design of block diagram, state diagram, flowchart, truth table
  • How to entry HDL for text based.
  • How to control of design management
  • How to write design document
  • How to create stimulus for simulation
  • How to simulation and debug
  • How to re-use legacy design
  • How to generate HDL from graphical entry
  • How to translate from the HDL text to the graphical design

Hands-on labs

  • Create new library
  • Create new graphical design of block diagram, state diagram, flowchart, truth table
  • Create stimulus
  • Simulation your design
  • Generate HDL from your design
  • Import legacy HDL design
  • Translate from the HDL text to the graphical design

Key topics

  • How to use Visual Elite
  • The specification of lab design
  • Start Visual Elite
  • Open library browser
  • Create new library
  • The editor common operation
  • Entry the block diagram
  • Entry the state diagram
  • Entry the flowchart
  • Entry truth table
  • Create the stimulus for simulation
  • Design check
  • Simulation and debug
  • Generate HDL
  • Import HDL
  • Translate the HDL text to graphical design

Course Information

Intended for

FPGA and ASIC Designers

CAD Engineers and Managers who will be responsible for integrating HDL Designer Series into their design flow

Members of CAD support groups who are responsible for increased productivity of FPGA and ASIC design teams


Basic knowledge of FPGA and ASIC and design techniques and procedures

Reading knowledge of HDL languages (VHDL or Verilog)

Familiarity with Windows NT, 2000, XP or Solaris and Redhat Linux operating systems

Course Part Number
  • Classroom: 232843

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